參數(shù)資料
型號： AM79C983AKC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 網(wǎng)絡接口
英文描述： Integrated Multiport Repeater 2 (IMR2⑩)
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP132
封裝： PLASTIC, QFP-132
文件頁數(shù)： 29/60頁
文件大?。?/td> 348K
代理商： AM79C983AKC
Am79C983A
29
P R E L I M I N A R Y
the incoming packet's source address with the Pre-
ferred Source Address Register. The interrupt is set
when there is a mismatch.
If the Automatic Intrusion Control register bit is set, the
port is disabled if there is no match between the source
address and either valid source address for that port.
Valid addresses are determined from the correspond-
ing Preferred Source Address Automatic Intrusion
Control Register and Last Source Address Automatic
Intrusion Control Register. The selection of these reg-
isters as valid addresses is made by the Last Source
Address Compare Enable Register and the Preferred
Source Address Compare Enable Register. The port is
disabled after the FCS field and only if the packet is a
valid packet. Once the port is disabled, it can only be
enabled by the management software.
Timer Values
Descriptions and values for the various timers are
as follows:
Microprocessor Interface
The IMR2 device implements a simple interface de-
signed to be used by a variety of available microproces-
sors. The bus interface is asynchronous and can be
easily adapted for different hardware interfaces.
The interface protocol is as follows:
1. Assert CS (LOW) and C/D (HIGH to access control
and LOW to access data).
2. Assert RD (LOW) to start a read cycle or WR (LOW)
to start a write cycle.
3. The IMR2 device forces RDY LOW in response to
the leading edge of either of RD or WR.
Note:
CS is internally gated with RD and WR, such
that CS may be permanently grounded if it is not re-
quired. A read or write cycle is started when CS and ei-
ther data strobe are asserted (LOW).
Write Cycle
:
1. Data is to be placed on the Data (D[7:0]) pins prior
to trailing edge of WR.
2. The IMR2 device releases RDY (pulled HIGH exter-
nally), indicating that it is ready to accept the data.
3. WR strobe is de-asserted (HIGH) in response to
RDY. The IMR2 device latches data internally on the
rising edge of WR.
4. The processor can stop driving Data pins after the
rising edge of the WR.
Many of the registers are two or more bytes long. In
these cases, the registers are read or written into by ac-
cessing the microprocessor port with C/D LOW the
same number of times as the byte size of the register.
Read Cycle
:
1. The IMR2 device drives Data pins.
2. The IMR2 device releases RDY (pulled HIGH), indi-
cating valid data.
3. De-assert RD (HIGH) in response to RDY HIGH.
4. The IMR2 device stops driving Data pins after the
trailing edge of RD.
The interrupt pin (INT) is an open drain output. It is OFF
(high impedance) upon reset, when all interrupts are
disabled (masked), or when all internal sources of the
interrupts are cleared. It is ON (LOW) when any of the
enabled interrupts occur. Reading all the internal regis-
ters that caused the interrupt clears the internal source
of the interrupt, and sets INT OFF.
Management Functions
All management functions are accessible through the
microprocessor interface. The functions are divided into
register banks which are subdivided into attribute regis-
ters. A register bank is selected by writing a byte with the
format 000P
4
P
3
P
2
P
1
P
0
into the C port, where P
4
through P
0
corresponds to the register bank. The de-
sired attribute register within the selected register bank
is selected by writing 111R
4
R
3
R
2
R
1
R
0
into the C port,
where R
4
through R
0
corresponds to the attribute regis-
ter. Data can then be read from or written to the D port.
For registers whose contents are cleared upon reading,
reading the first byte will clear the entire register. When
writing to registers, all bytes must be written consecu-
tively. If all register bytes are not written, the original
contents of the register are left unchanged.
Most of the registers contain status or control informa-
tion on the individual ports. These registers are each
two bytes long. Each bit corresponds to an individual
port. Active statistics will be maintained on the data
received by DAT only if the EP bit of the Port Enable
Register is set and MACEN is TRUE.
Tw1
Wait Timer for the end of
transmit recovery time
Wait Timer for the end of
carrier recovery time
Wait Timer for length of
continuous output
Wait Timer for time to disable
output for Jabber Lockup
Protection
Wait Timer for length of packet
without collision
Wait Timer for excessive
length of collision
Number of consecutive
collisions which must occur
before a segment (port) is
partitioned
10 bit times
Tw2
3 bit times
Tw3
65,536 bit times
Tw4
96 bit times
Tw5
452 to 523 bit
times
Tw6
2048 bit times
CC-
Limit
32 collisions
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