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參數(shù)資料
| 型號： | AM79C983AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | Integrated Multiport Repeater 2 (IMR2⑩) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 52/60頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AM79C983AKC |
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52
Am79C983A
P R E L I M I N A R Y
Notes:
1. Parameter is not tested.
2. ECLK is dependent on the frequency of the data on the active port.
3. (R)DI pulses narrower than tPWODI (min) will be rejected; (R)DI pulses wider than tPWODI (max) will turn internal (R)DI car-
rier sense on.
4. (R)DI pulses narrower than tPWKDI (min) will maintain internal (R)DI carrier sense on; (R)DI pulses wider than tPWKDI(max)
will turn internal (R)DI carrier sense off.
5. (R)CI pulses narrower than tPWOCI (min) will be rejected; (R)CI pulses wider than tPWOCI (max) will turn internal (R)CI car-
rier sense on.
6. (R)CI pulses narrower than tPWKCI (min) will maintain internal (R)CI carrier sense; (R)CI pulses longer than tPWKCI (max)
will turn internal (R)CI carrier sense off.
7. PDI pulses narrower than tPWOPDI (min) will be rejected; PDI pulses wider than tPWOPDI (max) will turn internal PDI carrier
sense on.
t
MHDR
t
MHDZ
t
MDSET
t
MDHOLD
t
MASET
t
MAHLD
t
ELDR
t
EDSET
t
EDHOLD
Microprocessor Interface Timing
t
CDS
C/D Setup Time with Respect to RD/WR
Leading Edge
t
CDH
C/D Hold Time with Respect to RD/WR Rising
Edge
t
CSS
CS Setup Time with Respect to RD/WR Fall-
ing Edge
t
CSH
CS Hold Time with Respect to RD/WR Rising
t
RDYD
RDY Leading Edge Delay
t
RDYH
RDY HIGH to RD/WR Rising
t
DOUT
Data Out to RDY HIGH
t
DOH
Data Out HOLD after RD HIGH
t
DIS
Data In Setup Time with Respect to WR Ris-
ing Edge
t
REST
Rest Period between MPI Operations (Time
between the Earliest CS/RD/WR Going HIGH
to the Next CS/RD/WR Going LOW, whichev-
er is the Latest
t
DIH
Data In HOLD after WR HIGH
MCLK HIGH to DAT/JAM Driven
MCLK HIGH TO DAT/JAM Not Driven
DAT/JAM Setup Time to MCLK
DAT/JAM Hold Time from MCLK
COL/ACK Setup Time to MCLK
COL/ACK Hold Time to MCLK
ECLK LOW to DAT Switching
DAT Setup to ECLK
DAT Hold Time from ECLK
C
L
=100pF
C
L
=100pF
10
14
10
10
5
14
-
10
14
40
40
-
-
-
-
20
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
=100pF
10
-
ns
0
-
ns
10
-
ns
0
-
0
50
10
25
-
ns
ns
ns
ns
ns
ns
C
L
=100pF
25
-
-
50
-
C
L
=100pF
C
L
=100pF
150
-
ns
0
-
ns
Management Port Timing
t
MSSO
MCLK to SDATA
t
MSDO
MCLK to DIR[1:0]
t
MSSSU
SDATA Setup Time
t
MSSHD
SDATA Hold Time
Packet Report Port Timing
t
PRV
PCLK LOW to PDAT Switching
10
10
10
10
40
40
-
-
ns
ns
ns
ns
-
20
ns
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AM79C983AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Integrated Multiport Repeater 2 (IMR2⑩) |
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| AM79C983KC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller |
| AM79C983SKC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller |
| AM79C984 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:enhanced Integrated Multiport Repeater (eIMR⑩) |
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