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參數(shù)資料
| 型號： | AM79C983AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | Integrated Multiport Repeater 2 (IMR2⑩) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 31/60頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AM79C983AKC |
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Am79C983A
31
P R E L I M I N A R Y
Total Octets
Address:
1110 1100
This is a 4-byte attribute register whose contents are in-
cremented while the repeater is repeating packet data.
This counter is a truncated divide by 8 of the total num-
ber of bits transmitted by the repeated (i.e., the number
of whole bytes transmitted by the repeater). The
counter counts the bytes on all non-collision packets
with a valid Start of Frame Delimiter (SFD). The pre-
amble is included in the count. The four bytes in this at-
tribute are sequentially accessed by reading the D
register, LSB first. Note that once the C register is pro-
grammed for access to this attribute, reading the D reg-
ister port causes the value of this register to be copied
into the holding register. The data is then read off the
holding register, without affecting this attribute. This se-
quence is repeated when the last byte is read and the
D register is accessed.
Transmit Collisions
Address:
1110 1101
This is a 4-byte attribute whose contents are incre-
mented each time the repeater has entered the trans-
mit collision state from any state other than ONE PORT
LEFT. The bytes are read in LOW to HIGH order by
reading the Data (D) register consecutively. The se-
quence will be restarted once the last byte is read or
the C register is reprogrammed with this register num-
ber. This causes the current value of the counter to be
copied into a holding register, which is then read by ac-
cessing the D register.
Configuration Register
Address:
This is a read/write register. The value read is the
same as that written. Unused bits are read as zeros
and only zeros should be written into these bits. Do
not write non-zero values into unused bits. All bits are
cleared upon reset.
1111 0000
I
Enable Interrupts
.
When this bit is set to 0 all inter-
rupts from this IMR2 device are masked (but not
cleared) and the INT output pin is forced into inac-
tive state (not driven).
Source Address Match Interrupt Enable. When this
bit is set, IMR2 device will generate an interrupt if
the Source Address of the received packet match-
es that which is programmed into the Source Ad-
dress Match Register.
Repeater Status
Address:
1111 1010
This is a read only register. Bit 0 is the only bit of inter-
est. When bit 0 is set, the IMR2 device has entered
MAU Jabber Lockup Protection (MJLP). The Repeater
Status register is cleared by reading.
S
E
Status
0
No Error
1
Error
QuIET Device Transceiver ID Register
Address:
1111 1011
This is a read-only register. It contains the transceiver
ID of the QuIET device connected to the IMR2 device.
The 16-bit quantity has the following format:
Transceiver 0
Transceiver 1
Transceiver 2
Transceiver 3
PAUI [3:0]
PAUI [7:4]
PAUI [11:8]
AUI and RAUI ports or misc.
This 16-bit register is divided into four sections. Each
section is labeled M
X3
to M
X0
where X refers to trans-
ceivers 0 through 3. These register bits are only valid if
the appropriate Transceiver Interface Status Register
bit indicates that a QuIET device is connected.
bit 7
bit 0
bit
31
bit
24
D Port Read/Write
M
SB
LSB
Byte 0
Byte 1
Byte 2
Byte 3
bit 7
bit 0
bit
31
MSB
bit 24
D Port Read/Write
LSB
Byte 0
Byte 1
Byte 2
Byte 3
I
0
S
0
0
0
0
0
D Port Read/Write
MSB
LSB
0
0
0
0
0
0
0
E
LSB
D Port Read
MSB
Transceiver 1
M
13
M
12
M
11
M
10
M
03
M
02
M
01
M
00
Transceiver 3
M
33
M
32
M
31
M
30
M
23
M
22
M
21
M
20
MSB
Transceiver 0
Transceiver 2
D Port Read
Byte 1
Byte 0
LSB
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