參數(shù)資料
型號(hào)： AMC1210IRHARG4
英文描述： Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
中文描述： 四數(shù)字濾波器2階Δ-Σ調(diào)制器
文件頁(yè)數(shù)： 41/47頁(yè)
文件大?。?/td> 805K
代理商： AMC1210IRHARG4
www.ti.com
CLK
x
SH1
or
SH2
Integrator
Accumulating Output from Digital Filter
Timer
Counting Digital filter samples
Time
Register
Data
Register
Integrator Data from period n
Period n
Period n+1
Timer Data from period n
Integrator Data from period n-1
Timer Data from period n-1
Over-Current Measurement
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Figure 26. Typical Integrator Sequence
Using the integrator with a digital filter provides improved noise performance for a marginal amount of delay. For
example, a Sinc
2
filter with an SOSR of 16, combined with an integrator with an IOSR of 64, offers three bits of
ENOB improvement at the cost of 1.6
μ
s delay.
The integrator and modulator can also be used together to calculate an average value of high bits (1) and low
bits (–1) coming from the modulator in a floating point factor between –1 and 1. Through bypassing the sinc filter
unit, the modulator output can be summed directly by the integrator. By setting up the timer and the integrator in
the same way as discussed in the previous example (TM = 1, IMOD = 1), an external signal (SHx) triggers the
integrator and timer to run simultaneously. Dividing the resulting integrator data by the time data generates a
value between –1 and 1. This calculation represents a ratio of high or low bits to the total number of samples,
where –1.0 is all low bits, 0.0 is an even number of high and low bits, and 1.0 is all high bits.
Configuring the AMC1210 for successful over-current measurement requires an understanding of the necessary
design conditions. The first parameter to keep in mind is the settling time. Once the user has established a
maximum settling time for an over-current event (the time between the over-current event and the first data
sample that exceeds the comparator threshold) that the system can tolerate, a corresponding digital filter can be
chosen.
Figure 27
shows settling times with the ADS1203 operating at 10MHz. As the allowable settling time is
increased, the amount of data that is filtered is increased, resulting in a higher ENOB. In this example, a
modulator rate of 10MHz is used. However, it should be noted that the user can also run the ADS1203 at
16MHz. This speed will decrease the settling time by a factor of 1.6; however, power consumption will be
increased.
41
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