參數(shù)資料
型號(hào): AMC1210IRHARG4
英文描述: Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
中文描述: 四數(shù)字濾波器2階Δ-Σ調(diào)制器
文件頁(yè)數(shù): 6/47頁(yè)
文件大?。?/td> 805K
代理商: AMC1210IRHARG4
www.ti.com
MODULATOR INPUT MODES
TIMING CHARACTERISTICS
Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, CVDD = +5V, BVDD = +2.7V, unless otherwise
noted.
Mode 0
CLKx
INx
t
su1
t
h1
t
w1
t
w2
CLKx
INx
Mode 1
t
su2
t
su2
t
h2
t
h2
t
w3
t
w4
Modulator internal clock
Modulator internal data
Mode 2
(Manchester-encoded bit stream)
1
0
1
1
0
0
1
1
1
t
w6
t
w5
INx
CLKx
INx
Mode 3
(CLKx is driven externally)
t
w7
t
w8
t
su3
t
h3
CLKx
INx
CLK
t
w11
Mode 3
(CLKx is generated by AMC1210)
t
d11
t
w12
t
d2
t
w10
t
w9
t
su4
t
h4
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
PARAMETER
MIN
MAX
UNIT
t
w1
t
w2
t
su1
t
h1
t
w3
t
w4
t
su2
t
h2
t
w5
t
w6
t
w7
t
w8
t
su3
t
h3
t
w9
Mode 0 clock period CLKx
45
1/64th of CLK period
ns
Mode 0 clock high time CLKx
10
t
w1
–10
ns
Setup time from data valid to CLKx high
5
ns
Hold time from CLKx high to data invalid
5
ns
Mode 1 clock period CLKx
90
1/128th of CLK period
ns
Mode 1 clock high time CLKx
20
t
w3
–10
ns
Setup time from data valid to CLKx high or low
5
ns
Hold time from CLKx high or low to data invalid
5
ns
Mode 2 data width INx
45
ns
Mode 2 data pulse width INx
22
ns
Mode 3 clock period CLKx
22
1/32nd of CLK period
ns
Mode 3 clock high time CLKx
5
t
w7
–5
ns
Setup time from data valid to any CLKx high
5
ns
Hold time from any CLKx high to data invalid
5
ns
System clock period CLK
11
ns
10
6
t
w10
t
w11
t
w12
t
d1
t
d2
t
su4
t
h4
System clock high time CLK
3
t
w9
–3
ns
Mode 3 generated clock period CLK
x
Mode 3 generated high time CLKx
t
w9
t
w9
x MD control bits
ns
t
w10
- 2
t
w10
+2
ns
Delay from system clock CLK high to generated CLKx high
0
3
ns
Delay from system clock CLK low to generated CLKx low
0
3
ns
Setup time from data valid to any CLKx high
5
ns
Hold time from any CLKx high to data invalid
5
ns
Figure 1. Modulator Input Mode Timing
6
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