參數(shù)資料
型號: AT40KEL040KW1SB
廠商: ATMEL CORP
元件分類: FPGA
英文描述: FPGA, 2304 CLBS, 50000 GATES, PQFP160
封裝: MQFP-160
文件頁數(shù): 8/42頁
文件大?。?/td> 670K
代理商: AT40KEL040KW1SB
16
AT40KEL040
4155G–AERO–05/05
Set/Reset Scheme
The AT40KEL040 family reset scheme is essentially the same as the clock scheme
except that there is only one Global Reset. A dedicated Global Set/Reset bus can be
driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks).
The automatic placement tool will choose the reset net with the most connections to use
the global resources. You can change this by using an RSBUF component in your
design to indicate the global reset. Additional resets will use the express bus network.
The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux,
there is Sector Set/Reset mux at every four cells. Each sector column of four cells is
set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux
(Figure 11 on page 17). The set/reset provided to each sector column of four cells is
either inverted or non-inverted using the Sector Reset mux.
The function of the Set/Reset input of a register is determined by a configuration bit in
each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or
Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a
high) is provided by each register (i.e., all registers are set at power-up).
相關(guān)PDF資料
PDF描述
AT40KEL040KZ1SB FPGA, 2304 CLBS, 50000 GATES, PQFP256
AT89C2051-12SCT/R 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO20
AT89C51-24JCT/R 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQCC44
AT89C55-12JA 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQCC44
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