參數(shù)資料
型號(hào)： AT42QT1110-AZ
廠商： ATMEL CORP
元件分類(lèi)： 速度傳感器和接近開(kāi)關(guān)
英文描述： PROXIMITY SENSOR-CAPACITIVE, 0-5V, SQUARE, SURFACE MOUNT
封裝： 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TQFP-32
文件頁(yè)數(shù)： 2/46頁(yè)
文件大?。?/td> 657K
代理商： AT42QT1110-AZ
10
9570I–AT42–03/10
AT42QT1110-MZ/AT42QT1110-AZ
4.
Detailed Operations
4.1
Communications
4.1.1
Introduction
All communication with the device is carried out over the Serial Peripheral Interface (SPI). This is
a synchronous serial data link that operates in full-duplex mode. The host communicates with
the QT controller over the SPI using a master-slave relationship, with the QT1110 acting in slave
mode.
4.1.2
SPI Operation
The SPI uses four logic signals:
Serial Clock (SCK) – output from the host.
Master Output, Slave Input (MOSI) – output from the host, input to the QT controller. Used by
the host to send data to the QT controller.
Master Input, Slave Output (MISO) – input to the host, output from the QT controller. Used by
the QT device to send data to the host.
Slave Select (SS) – active low output from the host.
At each byte, the master pulls SS low and generates 8 clock pulses on SCK. With these 8 clock
pulses, a byte of data is transmitted from the master to the slave over MOSI, most significant bit
(msb) first.
Simultaneously a byte of data is transmitted from the slave to the master over MISO, also most
significant bit first.
The slave reads the status of MOSI at the leading edge of each clock pulse, and the master
reads the slave’s data from MISO at the trailing edge.
The QT1110 requires that the clock idles “high”, meaning that the data on MOSI and MISO pins
are set at the falling edges and sampled at the rising edges.
That is:
Clock polarity CPOL = 1
Clock phase CPHA = 1
The QT1110 SPI interface can operate at any SCK frequency up to 1.5 MHz.
In multibyte communications, the master must pause for a minimum delay of 150 s between
the completion of one byte exchange and the beginning of the next.
Note that the number of bytes to be transmitted depends on the initial command sent by the
host. This sets the mode on the QT1110 so that the QT1110 knows how to respond to, or how to
interpret, the following bytes. If there is a delay of >100 ms between bytes while the QT1110 is
waiting for data, or waiting to send data, then the incomplete transmission is discarded and the
device resets its SPI state machine. It will then interpret the next byte it receives as a fresh
command.
When the QT1110 SPI interface is receiving a new command, it returns the “Idle” status code
(0x55) on MISO during the first byte exchange to indicate to the master that it is in the correct
state for receiving instructions.
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