參數(shù)資料
型號(hào): AT42QT1110-AZ
廠商: ATMEL CORP
元件分類: 速度傳感器和接近開(kāi)關(guān)
英文描述: PROXIMITY SENSOR-CAPACITIVE, 0-5V, SQUARE, SURFACE MOUNT
封裝: 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TQFP-32
文件頁(yè)數(shù): 41/46頁(yè)
文件大?。?/td> 657K
代理商: AT42QT1110-AZ
48
4519 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Table 12 A-D control registers
Q12
0
1
A-D operation mode selection bit
Analog input pin selection bits
Q11
0
1
0
1
A-D control register Q1
at RAM back-up : state retained
at reset : 00002
Q13
A-D conversion mode
Comparator mode
R/W
TAQ1/TQ1A
Q10
0
1
0
1
0
1
0
1
Q12
Q11
Q10
Analog input pins
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
P40, P41, P42, P43
AIN4, AIN5, AIN6, AIN7
P62, P63
AIN2, AIN3
P61
AIN1
P60
AIN0
P40/AIN4, P41/AIN5, P42/AIN6, P43/AIN7
pin function selection bit
P62/AIN2, P63/AIN3 pin function selection bit
P61/AIN1 pin function selection bit
P60/AIN0 pin function selection bit
0
1
0
1
0
1
0
1
Q23
Q22
Q21
Q20
R/W
TAQ2/TQ2A
A-D control register Q2
at RAM back-up : state retained
at reset : 00002
Note: “R” represents read enabled, and “W” represents write enabled.
Not used
A-D converter operation clock selection bit
A-D converter operation clock division
ratio selection bits
A-D control register Q3
Q33
Q32
Q31
Q30
at reset : 00002
at RAM back-up : state retained
0
1
0
1
Q31
0
1
Q30
0
1
0
1
Division ratio
Frequency divided by 6
Frequency divided by 12
Frequency divided by 24
Frequency divided by 48
This bit has no function, but read/write is enabled.
Instruction clock (INSTCK)
Ring oscillator (f(RING))
R/W
TAQ3/TQ3A
相關(guān)PDF資料
PDF描述
AT42QT1110-MZ PROXIMITY SENSOR-CAPACITIVE, 0-5V, SQUARE, SURFACE MOUNT
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