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參數(shù)資料
| 型號： | AT75C1010 |
| 英文描述： | AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems. |
| 中文描述： | AT75C1010電話軟件模塊[更新11/01。 29頁]本軟件模塊上運行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計所。擴(kuò)大其能力，使處理器的靈活和東部地區(qū)融入大多數(shù)操作系統(tǒng)。 |
| 文件頁數(shù)： | 46/171頁 |
| 文件大?。?/td> | 1288K |
| 代理商： | AT75C1010 |
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14
AT75C DSP Subsystem
1368C–INTAP–08/02
Data Address
Arithmetic Unit
(DAAU)
The DAAU performs all address storage and effective address calculations necessary to
address data operands in data and program memories and supports the software stack
pointer. In addition, it supports latching of the modified register in maximum/minimum
operations (see “Maximum/Minimum Operations” on page 9) and loop counter opera-
tions in conjunction with the MODR instruction (see “Instruction Set” on page 31) and
the R flag (see “Status Registers” on page 23). This unit operates in parallel with other
core resources to minimize address generation overhead. The DAAU performs two
types of arithmetics: linear and modulo. The DAAU contains six 16-bit address registers
(R0, R3 and R4, R5, also referred to as Rn) for indirect addressing, two 16-bit configura-
tion registers (CFGI and CFGJ) for modulo and increment/decrement step control and a
base register (RB) for supporting index addressing. In addition, it contains a 16-bit stack
pointer register (SP), alternative bank registers (R0B, R1B, R4B, CFGIB) supported by
an individual bank exchange and a 16-bit minimum-maximum pointer latching register
(MIXP, see “Maximum/Minimum Operations” on page 9). The Rn and configuration reg-
isters are divided into two groups for simultaneous addressing over XAB and YAB (or
PAB): R0, R3 with CFGI, and R4, R5 with CFGJ. Registers from both groups, in addition
to RB and SP, can be used for both XAB and YAB (or PAB) for instructions that use only
one address register. In addition, in these instructions the X-RAM and Y-RAM can be
viewed as a single continuous data memory space.
The R0, R1, R2, R3, R4, R5, CFGI, CFGJ, SP, RB and MIXP registers may be read
from or written to by the XDB as 16-bit operands, and thus can serve as general-pur-
pose registers.
Address Modification
The DAAU can generate two 16-bit addresses every instruction cycle, which can be
post-modified by two modifiers: linear and modulo. The address modifiers allow the cre-
ation of data structures in memory for circular buffers, delay lines, FIFOs, another
pointer to the software stack, etc. The Rn registers can also be used, in addition to the
block-repeat nesting, as loop counters in conjunction with the MODR instruction (see
“Instruction Set” on page 31) and the R flag of ST0 (see “Status Registers” on page 23).
Address modification is performed using 16-bit (modulo 65,536) 2’s complement linear
arithmetic. The range of values of the registers can be considered as signed (from -
32,768 to +32,767) or unsigned (from 0 to +65,535). This is also true for the data space
memory map. Index addressing capability is also available. For details, see “Index
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