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參數(shù)資料
| 型號： | AT75C1010 |
| 英文描述： | AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems. |
| 中文描述： | AT75C1010電話軟件模塊[更新11/01。 29頁]本軟件模塊上運行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計所。擴大其能力，使處理器的靈活和東部地區(qū)融入大多數(shù)操作系統(tǒng)。 |
| 文件頁數(shù)： | 94/171頁 |
| 文件大小： | 1288K |
| 代理商： | AT75C1010 |
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29
AT75C DSP Subsystem
1368C–INTAP–08/02
Internal Configuration
Register
The internal configuration register includes context-switching bits, the block-repeat indi-
cation and processor status bits.
Internal Configuration Register
BC2, BC1, BC0: Block-repeat Nesting Counter
Holds the current block-repeat loop nesting level as in the following:
The BCx bits are cleared during processor reset and due to disabling the block-repeat mechanism, by clearing
the LP bit.
The BCx bits are read-only.
LP: INLOOP
Set if a block-repeat is executed; cleared otherwise.
When transferring data into ICR, the LP bit will be influenced as follows:
1 – The LP bit and the block-repeat nesting counter are cleared.
0 – The LP bit is unaffected.
Clearing this bit causes a break from the four levels of block-repeat, hence clearing the block repeat nesting counter (BCx)
bits.
The inloop bit is cleared during processor reset.
The inloop bit can be cleared by writing to ICR.
In addition, refer to “Repeat and Block-repeat Unit” on page 18.
For breaking out from one block-repeat level, refer to the BREAK instruction in “Instruction Set” on page 31.
IC2, IC1, IC0, NMIC: Context Switching Enable
IC2 – INT2 Context switching enable
IC1 – INT1 Context switching enable
IC0 – INT0 Context switching enable
NMIC – NMI Context switching enable
Set – Enable context switching during the beginning of the corresponding interrupt.
Clear – Disable context switching during the beginning of the corresponding interrupt.
The ICx bits and NMIC are cleared during processor reset.
The ICx bits and NMIC can be modified by writing to ICR.
15
14
13
12
11
10
9
8
Reserved
76
54
32
10
BC2
BC1
BC0
LP
IC2
IC1
IC0
NMIC
BC2
BC1
BC0
Block-repeat Counter State Description
0
Not within a block-repeat loop
0
1
Within first block-repeat level (outer loop)
0
1
0
Within second block-repeat level
0
1
Within third block-repeat level
1
0
Within fourth block-repeat level (inner loop)
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