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參數資料
| 型號： | AT75C1010 |
| 英文描述： | AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems. |
| 中文描述： | AT75C1010電話軟件模塊[更新11/01。 29頁]本軟件模塊上運行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計所。擴大其能力，使處理器的靈活和東部地區(qū)融入大多數操作系統(tǒng)。 |
| 文件頁數： | 50/171頁 |
| 文件大小： | 1288K |
| 代理商： | AT75C1010 |
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143
AT75C DSP Subsystem
1368C–INTAP–08/02
The TRAP instruction should not be used within another TRAP/BI interrupt service
routine.
The TRAP/BI service routine must end with a reti or retid instruction.
The on-chip emulation module (OCEM) uses the BI to provide emulation capability
within the OakDSPCore. When BI is used as hardware interrupt, note the following dif-
ferences between BI and other interrupts:
The latency is two instruction cycles (compared to one in other interrupts)
BI has the highest priority
BI has no masking option
BI has no option for automatic context switching
Interrupt Latency
The INT0, INT1, INT2 interrupts latency is one machine cycle, assuming that the OakD-
SPCore is in an interruptible state. The BI latency is two machine cycles, assuming that
the OakDSPCore is in an interruptible state. During non-interruptible states, the OakD-
SPCore will not service the interrupt, but will continue to execute instructions. The
interrupt will be accepted once the OakDSPCore exits this state.
Non-interruptible states are:
during reset
during the first three instruction fetches after de-activation of the reset. BI is an
exception.
during the execution of multi-cycle instructions
when no clock is provided to the DSP subsystem
during a nested repeat loop execution
For specific instructions where interrupts are delayed after their execution, refer to the
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