參數(shù)資料
型號: AT75C1010
英文描述: AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems.
中文描述: AT75C1010電話軟件模塊[更新11/01。 29頁]本軟件模塊上運行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計所。擴大其能力,使處理器的靈活和東部地區(qū)融入大多數(shù)操作系統(tǒng)。
文件頁數(shù): 79/171頁
文件大?。?/td> 1288K
代理商: AT75C1010
17
AT75C DSP Subsystem
1368C–INTAP–08/02
using the PUSH and POP instructions. The top of stack can be read without affecting SP
using a dedicated MOV instruction.
The software stack can reside anywhere in the data space (X-RAM and Y-RAM) and
can be accessed by any other pointer (R0 to R5 and RB).
The software stack is useful for supporting the C-compiler. The stack can be used for
transferring routine parameters (e.g., C-automatic variables). Thus, after initializing the
base register (RB) by the SP value, the routine parameters can be referenced by the
index mode with the MOV, ADD, SUB, CMP, AND, OR and XOR instructions. Another
support for transfer of routine parameters is the RETS instruction, which returns from a
subroutine and updates the SP by a short immediate value.
The SP register is part of the global register set. Refer to “Programming Model and Reg-
Alternative Bank of
Registers
The DAAU contains an alternative bank of four registers: R0B, R1B, R4B, CFGIB. For
each of the R0/R0B, R1/R1B, R4/R4B or CFGI/CFGIB, only one register is accessible at
a time. The selection between the current or the alternative register is controlled by a
special BANKE instruction, which exchanges (swaps) the contents between the current
register with the alternative bank register.
The bank exchanging is selected individually, meaning that the BANKE instruction
includes a list of registers to be exchanged in a single cycle. For the four registers there
are 15 different options. Refer to BANKE instruction in “Instruction Set” on page 31.
The individual selectivity of the bank registers contributes to flexibility of the bank regis-
ters. The user can decide where each of the alternative registers will be utilized in
interrupts, routines, etc.
Program Control Unit
(PCU)
The Program Control Unit (PCU) performs instruction fetch, instruction decoding, excep-
tion handling, hardware loop control, wait state support and on-chip emulation support.
In addition, it controls the internal program memory protection. Refer to “Program
The PCU contains the Repeat/Block-repeat unit and two 16-bit directly accessible regis-
ters: the Program Counter (PC) and the Loop Counter (LC).
The PCU selects and/or calculates the next address from several possible sources:
the incremented PC in sequential program flow
jump address in branch or call operations
short PC-relative address of seven bits in relative branch or call operations
start address and exit address of hardware loops
interrupts vector handling
user write to PC or the top value on the stack, pointed to by the SP register upon
returning from subroutines and interrupts
The PCU also writes the PC to the top of stack in subroutines and interrupts.
The PC always contains the address of the next instruction.
For more information on the pipeline method, refer to “Pipeline Method” on page 140.
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