參數(shù)資料
型號： AT89C51ED2-SMRUM
廠商： Atmel
文件頁數(shù)： 121/137頁
文件大小： 0K
描述： IC MCU FLASH 8051 64K 5V 68PLCC
產品培訓模塊： MCU Product Line Introduction
標準包裝： 1
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 60MHz
連通性： SPI，UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 50
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-PLCC
包裝： 標準包裝
其它名稱： AT89C51ED2-SMRUMDKR
84
4235K–8051–05/08
AT89C51RD2/ED2
19. Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT
(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user
must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is
enabled, it will increment every machine cycle while the oscillator is running and there is no way
to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
19.1
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-
tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to
WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)
and this will reset the device. When WDT is enabled, it will increment every machine cycle while
the oscillator is running. This means the user must reset the WDT at least every 16383 machine
cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write
only register. The WDT counter cannot be read or written. When WDT overflows, it will generate
an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where
TCLK PERIPH= 1/FCLK PERIPH. To make the best use of the WDT, it should be serviced in those sec-
tions of code that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability,
ranking from 16 ms to 2s @ FOSCA = 12 MHz. To manage this feature, refer to WDTPRG register
description, Table 19-1. The WDTPRG register should be configured before the WDT activation
sequence, and can not be modified until next reset.
Table 19-1.
WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
7
6
5
4
3
2
1
0
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相關代理商/技術參數(shù)
參數(shù)描述
AT89C51ED2-SMSIM 制造商:Atmel Corporation 功能描述:MCU 8-bit AT89 80C51 CISC 64KB Flash 3.3V/5V 68-Pin PLCC Stick 制造商:Atmel/Adesto Technologies 功能描述:Bulk 制造商:Atmel Corporation 功能描述:AT89C51ED2-SMSIM 8bit microcontroller
AT89C51ED2-SMSUM 功能描述:8位微控制器 -MCU C51ED2 64K FLASH 3-5.5V Ind RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C51ED2-UM 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller
AT89C51IC2 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller with 2-wire Interface
AT89C51IC2_04 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller with 2-wire Interface
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