參數(shù)資料
型號: AT89C51ED2-SMRUM
廠商: Atmel
文件頁數(shù): 47/137頁
文件大?。?/td> 0K
描述: IC MCU FLASH 8051 64K 5V 68PLCC
產(chǎn)品培訓模塊: MCU Product Line Introduction
標準包裝: 1
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 50
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-PLCC
包裝: 標準包裝
其它名稱: AT89C51ED2-SMRUMDKR
17
4235K–8051–05/08
AT89C51RD2/ED2
7.
Enhanced Features
In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new features,
which are:
X2 option
Dual Data Pointer
Extended RAM
Programmable Counter Array (PCA)
Hardware Watchdog
SPI interface
4-level interrupt priority system
Power-off flag
ONCE mode
ALE disabling
Some enhanced features are also located in the UART and the Timer 2
7.1
X2 Feature
The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature called
‘X2’ provides the following advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically the operating frequency by 2 in operating
and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
7.1.1
Description
The clock for the whole circuit and peripherals is first divided by two before being used by the
CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 7-1 shows the clock generation block diagram. X2 bit is validated on the rising edge of
the XTAL1 ÷ 2 to avoid glitches when switching from X2 to STD mode. Figure 7-2 shows the
switching mode waveforms.
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