參數(shù)資料
型號: AT89C51ED2-SMRUM
廠商: Atmel
文件頁數(shù): 134/137頁
文件大小: 0K
描述: IC MCU FLASH 8051 64K 5V 68PLCC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標準包裝: 1
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 50
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-PLCC
包裝: 標準包裝
其它名稱: AT89C51ED2-SMRUMDKR
96
4235K–8051–05/08
AT89C51RD2/ED2
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the applica-
tion to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 24-4 and Table 24-5.
To assure code protection from a parallel access, the HSB must also be at the required level.
Table 24-4.
Software Security Byte
The two lock bits provide different levels of protection for the on-chip code and data, when pro-
grammed as shown in Table 24-5.
BSB
Boot Status Byte
0FFh
SSB
Software Security Byte
FFh
Copy of the Manufacturer Code
58h
Atmel
Copy of the Device ID #1: Family Code
D7h
C51 X2, Electrically Erasable
Copy of the Device ID #2: Memories Size and
Type
ECh
AT89C51RD2/ED2 64KB
Copy of the Device ID #3: Name and Revision
EFh
AT89C51RD2/ED2 64KB,
Revision 0
7
6
5
4
3
2
1
0
-
LB1
LB0
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
Do not clear this bit.
6
-
Reserved
Do not clear this bit.
5
-
Reserved
Do not clear this bit.
4
-
Reserved
Do not clear this bit.
3
-
Reserved
Do not clear this bit.
2
-
Reserved
Do not clear this bit.
1-0
LB1-0
User Memory Lock Bits
Mnemonic
Definition
Default value
Description
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