參數(shù)資料
型號: AT89LP428-20PU
廠商: Atmel
文件頁數(shù): 17/149頁
文件大?。?/td> 0K
描述: MCU 8051 4K FLASH SPI 28PDIP
產品培訓模塊: MCU Product Line Introduction
標準包裝: 14
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
113
3654A–MICRO–8/09
AT89LP428/828
22. On-chip Debug System
The AT89LP428/828 On-chip Debug (OCD) System uses a 2-wire serial interface to control pro-
gram flow; read, modify, and write the system state; and program the nonvolatile memory. The
OCD System has the following features:
Complete program flow control
Read-modify-write access to all internal SFRs and data memories
Four hardware program address breakpoints
Unlimited program software breakpoints using BREAK instruction
Break on change in program memory flow
Break on stack overflow/underflow
Break on Watchdog overflow
Break on reset
Non-intrusive operation
Programming of nonvolatile memory
22.1
Physical Interface
The On-chip Debug System uses a 2-wire synchronous serial interface to establish communica-
tion between the target device and the controlling emulator system. The OCD interface is
controlled by two User Fuses. OCD is enabled by clearing the OCD Enable Fuse. The OCD
device connections are shown in Figure 22-1. When OCD is enabled, the RST port pin is config-
ured as an input for the Debug Clock (DCL). Either the XTAL1, XTAL2 or P3.7 pin is configured
as a bi-directional data line for the Debug Data (DDA) depending on the clock source selected. If
the Internal RC Oscillator is selected, XTAL1 is configured as DDA (A). If the External Clock is
selected, XTAL2 is configured as DDA (B). If the Crystal Oscillator is selected, P3.7 is config-
ured as DDA (C). When OCD is enabled, the type of interface used depends on the OCD
Interface Select User Fuse. This fuse selects between a normal Two-wire Interface (TWI) and a
fast Two-wire Interface (FTWI). It is the duty of the user to program this fuse to the correct set-
ting for their debug system at the same time they enable OCD (see “User Configuration Fuses”
When designing a system where On-chip Debug will be used, the following observations must
be considered for correct operation:
P3.6/RST cannot be connected directly to V
CC and any external capacitors connected to RST
must be removed.
All external reset sources must be removed.
If P3.7 needs to be debugged in-system using the crystal oscillator, the external clock option
should be selected. The quartz crystal and any capacitors on XTAL1 or XTAL2 must be
removed and an external clock signal must be driven on XTAL1. Some emulator systems may
provide a user-configurable clock for this purpose.
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