參數(shù)資料
型號(hào): AT89LP428-20PU
廠商: Atmel
文件頁(yè)數(shù): 3/149頁(yè)
文件大小: 0K
描述: MCU 8051 4K FLASH SPI 28PDIP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 14
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
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100
3654A–MICRO–8/09
AT89LP428/828
18.1
Analog Input Muxes
The positive input terminal of each comparator may be connected to any of the four analog input
pins by changing the CSA
1-0 or CSB1-0 bits in ACSRA and ACSRB. When changing the analog
input pins, the comparator must be disconnected from its inputs by clearing the CONA or CONB
bits. The connection is restored by setting the bits again after the muxes have been modified.
CLR
EC
; Disable comparator interrupts
ANL
ACSRA, #0DFh
; Clear CONA to disconnect COMP A
...
; Modify CSA or RFA bits
ORL
ACSRA, #020h
; Set CONA to connect COMP A
ANL
ACSRA, #0EFh
; Clear any spurious interrupt
SETB
EC
; Re-enable comparator interrupts
The corresponding comparator interrupt should not be enabled while the inputs are being
changed, and the comparator interrupt flag must be cleared before the interrupt is re-enabled in
order to prevent an unintentional interrupt request.
18.2
Internal Reference Voltage
The negative input terminal of each comparator may be connected to an internal voltage refer-
ence by changing the RFB
1-0 or RFA1-0 bits in AREF. The internal reference voltage, VAREF, is
set to 1.25V ±5%. The voltage reference also provides two additional voltage levels approxi-
mately 125 mV above and below V
AREF. These levels may be used to configure the comparators
as an internally referenced window comparator with up to four input channels. Changing the ref-
erence input must follow the same routine used for changing the positive input as described in
18.3
Comparator Interrupt Debouncing
The comparator output is normally sampled every clock cycle. The conditions on the analog
inputs may be such that the comparator output will toggle excessively. This is especially true if
applying slow moving analog inputs. Three debouncing modes are provided to filter out this
noise for edge-triggered interrupts. In debouncing mode, the comparator uses Timer 1 to modu-
late its sampling time when CxC
1-0 = 00B. When a relevant transition occurs, the comparator
waits until two Timer 1 overflows have occurred before resampling the output. If the new sample
agrees with the expected value, CFx is set. Otherwise, the event is ignored. The filter may be
tuned by adjusting the time-out period of Timer 1. Because Timer 1 is running free, the
debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 time-out
period. Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out
periods later. See Figure 18-2. When the comparator clock is provided by one of the timer over-
flows, i.e. CxC
1-0 = 00B, any change in the comparator output must be valid after 4 samples to
be accepted as an edge event.
Figure 18-2. Negative Edge with Debouncing Example
Comparator Out
Timer 1 Overflow
CFx
Start
Compare
(rejected)
Compare
(accepted)
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