參數(shù)資料
型號: ATMEGA328P-15MZ
廠商: Atmel
文件頁數(shù): 22/83頁
文件大?。?/td> 0K
描述: MCU AVR 32K FLASH 15MHZ 32-QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 32-VFQFN 裸露焊盤
包裝: 剪切帶 (CT)
其它名稱: ATMEGA328P-15MZCT
PIC12(L)F1822/PIC16(L)F1823
DS41413C-page 188
2010-2012 Microchip Technology Inc.
21.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 21-2, is used to control Timer1 Gate.
REGISTER 21-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W/HC-0/u
R-x/x
R/W-0/u
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
TMR1GE:
Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1
= Timer1 counting is controlled by the Timer1 gate function
0
= Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL:
Timer1 Gate Polarity bit
1
= Timer1 gate is active-high (Timer1 counts when gate is high)
0
= Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM:
Timer1 Gate Toggle Mode bit
1
= Timer1 Gate Toggle mode is enabled
0
= Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM:
Timer1 Gate Single-Pulse Mode bit
1
= Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0
= Timer1 gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE:
Timer1 Gate Single-Pulse Acquisition Status bit
1
= Timer1 gate single-pulse acquisition is ready, waiting for an edge
0
= Timer1 gate single-pulse acquisition has completed or has not been started
bit 2
T1GVAL:
Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>:
Timer1 Gate Source Select bits
00
= Timer1 Gate pin
01
= Timer0 overflow output
10
= Comparator 1 optionally synchronized output (SYNCC1OUT)
11
= Comparator 2 optionally synchronized output (SYNCC2OUT)
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