參數(shù)資料
型號(hào)： ATMEGA328P-15MZ
廠商： Atmel
文件頁(yè)數(shù)： 43/83頁(yè)
文件大小： 0K
描述： MCU AVR 32K FLASH 15MHZ 32-QFN
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 1
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
包裝： 剪切帶 (CT)
其它名稱： ATMEGA328P-15MZCT
PIC12(L)F1822/PIC16(L)F1823
DS41413C-page 206
2010-2012 Microchip Technology Inc.
24.1
Capture Mode
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCP1 pin, the
16-bit CCPR1H:CCPR1L register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCP1M<3:0> bits of
the CCP1CON register:
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCP1IF of the PIR1 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPR1H, CCPR1L register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 24-1 shows a simplified diagram of the Capture
operation.
24.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCP1 pin function may be moved to
alternative pins using the APFCON register. Refer to
for more
details.
FIGURE 24-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
24.1.2
TIMER1 MODE RESOURCE
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP1 module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
for more information on configuring Timer1.
24.1.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit of the PIE1 register clear to
avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR1 register
following any change in Operating mode.
24.1.4
CCP1 PRESCALER
There are four prescaler settings specified by the
CCP1M<3:0>
bits
of
the
CCP1CON
register.
Whenever the CCP1 module is turned off, or the CCP1
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCP1CON register before changing the
prescaler. Example 24-1 demonstrates the code to
perform this function.
EXAMPLE 24-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
Note:
If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set Flag bit CCP1IF
(PIR1 register)
Capture
Enable
CCP1M<3:0>
Prescaler
1, 4, 16
and
Edge Detect
pin
CCP1
System Clock (FOSC)
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCP1
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
BANKSEL CCP1CON
;Set Bank bits to point
;to CCP1CON
CLRF
CCP1CON
;Turn CCP1 module off
MOVLW
NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP1 ON
MOVWF
CCP1CON
;Load CCP1CON with this
;value
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