參數(shù)資料
型號: C9812DYB
英文描述: Up to 5A ULDO linear regulator
中文描述: CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料
文件頁數(shù): 11/18頁
文件大?。?/td> 268K
代理商: C9812DYB
Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 11 of 18
APPROVED PRODUCT
C9812
AC Parameters
133 MHz Host
Min
7.5
1.87
1.67
0.4
-
-
60.0
25.5
25.3
0.4
-
15.0
5.25
5.05
0.4
-
-
30.0
12.0
12.0
0.5
-
100 MHz Host
Min
10.0
3.0
2.8
0.4
-
-
60.0
25.5
25.3
0.4
-
15.0
5.25
5.05
0.4
-
-
30.0
12.0
12.0
0.5
-
Symbol
Parameter
Max
8.0
-
-
1.6
175
250
-
-
-
1.6
500
16.0
-
-
1.6
250
500
-
-
-
2.0
500
Max
10.5
-
-
1.6
175
250
-
-
N/S
1.6
500
16.0
-
-
1.6
250
500
-
-
-
2.0
500
Units
Notes
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
CPU(0:1) period
CPU(0:1) high time
CPU(0:1) low time
CPU(0:1) rise and fall times
CPU0 to CPU1 Skew time
CPU(0:1) Cycle to Cycle Jitter
APIC(0:1) period
APIC(0:1) high time
APIC(0:1) low time
APIC(0:1) rise and fall times
APIC(0:1) Cycle to Cycle Jitter
3V66-(0:1) period
3V66-(0:1) high time
3V66-(0:1) low time
3V66-(0:1) rise and fall times
3V66-0 to 3V66-1 Skew time
3V66-(0:1) Cycle to Cycle Jitter
PCI(0:7) period
PCI(0:7) period
PCI(0:7) low time
PCI(0:7) rise and fall times
(Any PCI clock) to (Any PCI clock)
Skew time
PCI(0:7) Cycle to Cycle Jitter
48MHz period ( conforms to
+167ppm max)
48MHz rise and fall times
48MHz Cycle to Cycle Jitter
REF period
REF rise and fall times
REF Cycle to Cycle Jitter
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
nS
nS
nS
nS
pS
pS
nS
nS
nS
nS
pS
nS
nS
nS
nS
pS
pS
nS
nS
nS
nS
pS
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
TCCJ
TPeriod
-
500
-
500
pS
nS
6, 8, 9
5, 6, 8
20.8299
20.8333
20.8299
20.8333
Tr / Tf
TCCJ
TPeriod
Tr / Tf
TCCJ
tpZL, tpZH
tpLZ, tpZH
tstable
1.0
-
4.0
500
71.0
4.0
1000
10.0
10.0
3
1.0
-
4.0
500
71.0
4.0
1000
10.0
10.0
3
nS
pS
nS
nS
pS
nS
nS
mS
6, 7
6, 8, 9
5, 6, 8
6, 7
6, 8
13
13
12
69.8413
1.0
-
1.0
1.0
69.8413
1.0
-
1.0
1.0
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