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參數(shù)資料
| 型號： | C9812DYB |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 268K |
| 代理商： | C9812DYB |
Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 5 of 18
APPROVED PRODUCT
C9812
Power on Bi-Directional Pins
Power Up Condition:
Pin1 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of
the device, this pin is in input mode (see Fig 4, below), therefore; it is
considered an input select pins internal to the IC.
After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output.
-
Hi-Z INPUTS
TOGGLE OUTPUTS
POWER SUPPLY
RAMP
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL
Fig.4
REF / SEL2
(Pin 1)
VDD RAIL
Strapping Resistor Options:
The power up bi-directional pins have a large value pull-down each (70K
)
, therefore, a selection “0” is the default. If the
system uses a slow power supply (over 5mS settling time), then
it is recommended
to use an external Pull-down in
order to insure a low selection.
Fig. 5 If a selection “0” is desired, then a jumper is placed on JP1 to a 10K
resistor as implemented as shown in Fig.5.
Please note the selection resistor (Rdn
)
is placed before the Damping resistor (Rd) close to the pin.
Load
Fig. 5
Vdd
JP1
Jumper
Rsel
10K
Rd
IMI C9812
Bidirectional
70K
1
2
3
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