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參數(shù)資料
| 型號： | C9812DYB |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 268K |
| 代理商： | C9812DYB |
Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 15 of 18
APPROVED PRODUCT
C9812
Suggested Crystal Oscillator Parameters
Characteristic
Symbol
Frequency
F
o
Tolerance
TC
TS
TA
Mode
OM
Load Capacitance
CL
Effective Series
resistance (ESR)
Power Dissipation
DL
Shunt Capacitance
CO
Min
12.00
-
-
-
-
-
-
Typ
Max
16.00
+/-100
+/- 100
5
-
-
-
Units
MHz
PPM
PPM
PPM
Conditions
14.31818
-
-
-
-
18
40
Note 1
Stability (Ta -10 to +60C) Note 1
Aging (first year @ 25C) Note 1
Parallel Resonant, Note 1
The crystal’s rated load. Note 1
Note 1
pF
R1
Ohms
-
-
-
0.10
8
mW
pF
Note 1
Crystal’s internal package
capacitance (total)
--
Note1: For best performance and accurate Center frequencies of this device, It is recommended but not mandatory that
the chosen crystal meets these specifications
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Device pin capacitance: Cxtal = 34pF
In order to meet the specification for CL = 18pF following the formula:
Then the board trace capacitance between Xin and the crystal should be no more than 2pF. (same is applicable to the
trace between Xout and the crystal)
In this case the total capacitance from the crystal to Xin will be 36pF. Similarly the total capacitance between the crystal
and Xout will be 36pF. Hence using the above formula:
XOUT
XIN
XOUT
C
XIN
L
C
xC
+
C
C
=
pF
pF
pF
pF
pFx
C
L
18
36
36
36
+
36
=
=
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