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參數(shù)資料
| 型號： | C9812DYB |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 268K |
| 代理商： | C9812DYB |
Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 12 of 18
APPROVED PRODUCT
C9812
Switching Characteristics
Characteristic
Output Duty Cycle
CPU to SDRAM
CPU to 3V66
SDRAM to 3V66
3V66 to PCI
PCI to IOAPIC
Skew (CPU0-CPU1)
Skew (SDRAM-SDRAM)
Skew (APIC-APIC)
Skew (3V66-3V66)
Skew (PCI – PCI)
Cycle to Cycle Jitter
Cycle to Cycle Jitter
Symbol
Min
45
Typ
50
Max
Units
Conditions
-
55
500
500
500
-
1
175
250
250
175
500
250
500
%
pS
pS
pS
nS
nS
pS
pS
pS
pS
pS
pS
pS
Note 6
TPD1
TPD2
TPD3
tPD
tPD
tSKEW1
tSKEW2
tSKEW3
tSKEW4
TSKEW5
P1
P2
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
CPU = 133.3MHz, Notes 6, 7
CPU = 133.3MHz, Notes 6, 7
CPU = 66.6/100/133.3MHz Notes 6, 7
CPU = 66.6/100/133.3MHz Notes 6, 7
CPU = 66.6/100/133.3MHz Notes 6, 7
see Notes 6, 7
see Notes 6, 7
1.5
-
-
-
-
-
-
-
-
CPU, and SDRAM, Notes 6 & 7
IOAPIC, USB, DOT, 3V66, PCI,
Notes 6, 7
REF, Notes 6& 7
Cycle to Cycle Jitter
P3
-
-
1,000
pS
VDD=VDDS=3.3V
±
5%, VDDC=VDDI=2.5
±
5%, TA=0 to 70oC
All outputs loaded as per table 5 below. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for 2.5V
signals.
This measurement is applicable with Spread Spectrum ON or OFF.
Note 6:
Note 7:
Output Buffer Characteristics
Buffer Characteristics for CPU
Characteristic
Pull-Up Current
Pull-Up Current
Pull-Down Current
Pull-Down Current
Dynamic Output Impedance
Rise Time Min
Between 0.4 and 2.0 V
Fall Time Max
Between 0.4 and 2.0 V
Symbol
IOH
1
IOH
2
IOL
1
IOL
1
Min
-28
-26
12
27
13.5
0.4
Typ
-61
-58
24
56
Max
-107
-101
40
93
45
1.6
Units
mA
mA
mA
mA
Conditions
Vout =VDDC - 0.4V
Vout = 1.2 V
Vout = 0.4 V
Vout = 1.2 V
Z0
Tr
nS
-
20pF Load
Tf
0.4
-
1.6
nS
20pF Load
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