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參數(shù)資料
| 型號： | C9812DYB |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 268K |
| 代理商： | C9812DYB |
Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 2 of 18
APPROVED PRODUCT
C9812
Pin Description
PIN No.
1
Pin Name
SEL2/REF
PWR
VDD
I/O
I/O
TYPE
Description
3.3V 14.318 MHz clock output.
This pin also serves as the select strap (associates with SEL0 &
1, see app. note page 5) for clock frequencies during power up.
Refer to Table 1 for detail. This pin has an internal pull-down
(Typ. 70K
).
14.318MHz Crystal input
14.318MHz Crystal output
3.3V PCI clock outputs
3
4
11, 12, 13,
15, 16, 18,
19, 20
7, 8
25
26
28, 29
XIN
XOUT
PCI0/ICH
PCI(1..7)
VDD
VDD
VDD
I
OSC1
O
O
3V66(0,1)
USB
DOT
SEL(0,1)
VDD
VDD
VDD
VDD
O
O
O
I
3.3V Fixed 66.6 MHz clock outputs
3.3V Fixed 48 MHz clock outputs
3.3V Fixed 48 MHz clock outputs
3.3V LVTTL compatible inputs for logic selection. Has an
internal pull-up (Typ. 250K
)
I2C compatible SDATA input. Has an internal pull-up (>100K
)
I2C compatible SCLK input. Has an internal pull-up (>100K
)
3.3V LVTTL compatible input. Device enters powerdown mode
When held LOW. Has an internal pull-up (>100K
)
3.3V output running 100MHz
3.3V output running 100MHz. All SDRAM outputs can be turned
off through SMBUS.
30
31
32
SDATA
SCLK
PD#
VDD
VDD
VDD
I
I
I
34
36, 37, 39,
40, 42, 43,
45, 46
49, 50, 52
DCLK
SDRAM(7..0)
VDD
VDDS
O
O
CPU(2)_ITP,
CPU(1,0)
IOAPIC(1,0)
VDDC
O
2.5V Host bus clock outputs. 66, 100 or 133MHz depending on
state of SEL(2..0)
2.5V clock outputs running rising edge synchronous with the
PCI clock.
3.3V Power Supply
54, 55
VDDI
O
2, 9, 10, 21,
27, 33
22
23
51, 53
5, 6,14, 17,
24, 35, 41,
47, 48, 56
38, 44
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
VDD
-
VDDA
VSSA
VDDC, VDDI
VSS
-
-
-
-
Analog circuitry 3.3V Power Supply
Analog circuitry power supply Ground pins.
2.5V Power Supply’s
Common Ground pins.
-
VDDS
-
-
3.3V power support for SDRAM clock output drivers.
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