參數(shù)資料
型號(hào)： CA95C09-33CT
元件分類： 加密電路
英文描述： TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44
封裝： TQFP-44
文件頁(yè)數(shù)： 18/42頁(yè)
文件大?。?/td> 180K
代理商： CA95C09-33CT
Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-49
In one-bit cipher feedback mode, if a single byte is written to
the Input Register (when requested by the DCP via the Input
Flag) then the ciphering algorithm unit will remain busy
until all bits in the Input Register, corresponding to set bits in
the Mask Register, are processed. For example, if the Mask
Register is set to “01101001” and the Mode Register's CFB-
1 Mask Direction bit is set for MSB to LSB Mask
interpretation,
then
the
DCP
will
perform
Encryption/Decryption on bit 6 of the Input Register,
followed by bits 5, 3, and 1. The corresponding results will
be placed in bits 6, 5, 3 and 1 of the Output Register. All
other bits in the Input Register will be ignored and all other
bits in the Output Register will be set to the state indicated
by the Default Output bit (M6) of the Mode Register. The
ciphering algorithm unit will remain busy until all four bits
are ciphered. Zero to eight bits of the Mask Register may be
set to “1”. If zero bits are set to “1” then any subsequent
writes to the Input Register will be ignored.
Figure 3-16 : Mode Register Bit Assignments
M6
M7
M5 M4 M3 M2 M1 M0
}
Reserved
Encrypt/Decrypt
1 = Encrypt
0 = Decrypt
Cipher Type
00 = Electronic Code Book (ECB) (default)
01 = 8-bit Cipher Feedback (CFB-8)
10 = Cipher Block Chaining (CBC)
11 = 1-bit Cipher Feedback (CFB-1)1
Port Configuration
00 = Dual Port, Master Encrypted, Slave Clear
01 = Dual Port, Master Clear, Slave Encrypted (default)
10 = Single Port, Master Only
11 = Reserved
*CFB-1 Mask Direction
0 = MSB to LSB
1
(default)
1 = LSB to MSB
* The CFB-1 Mask Direction and Default Output bits are only accessible when the
DCP is in CFB-1 mode, otherwise these bits are high.
1.) This mode is Newbridge Microsystems specific.
*CFB-1 Default Ouput
1 = Masked output bits
are set (default)
0 = Masked output bits are
cleared1
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