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參數(shù)資料
| 型號： | CA95C09-33CT |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 42/42頁 |
| 文件大小： | 180K |
| 代理商： | CA95C09-33CT |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-33
10
11
5
O
Auxiliary Port Flag: This active LOW output signal indicates that the DCP is
expecting key-data to be entered on the Auxiliary Port Bus. This can occur
only when C/K is LOW (Multiplexed Control Mode) and a Load Key Through
AUX Port command has been entered.
will remain active (LOW)
during input of all eight bytes, and will go inactive with the falling edge of the
eighth
.
12
13
14
8
O
Parity: The DCP checks all key bytes for correct (odd) parity as they are
entered through either the Master Port (Multiplexed or Direct Control Mode)
or the Auxiliary Port (Multiplexed Control Mode only). If any key byte contains
even parity, the PAR bit in the Status Register is set to a “1” and
goes
active (LOW). (See Parity Checking of Keys.). The Parity bit is the least
signicant bit of the key byte.
OPTION
––139
I
Option: (For CA95C09) This input allows the user to congure the Master
Port Control interface to function as either a CA95C68 or a CA95C18. When
the OPTION pin is tied to VDD, the device will function with the interface of a
CA95C68. Conversely, tying the OPTION pin to VSS will cause the DCP to
function as a CA95C18. This OPTION pin must be tied to either VSS or VDD,
or erratic operation of the device will occur. The CA95C09 DCP will perform
identically to the CA95C68 or the CA95C18 (depending on the OPTION pin)
with the only difference being the order of the signal names on the device
package.
VDD
40
44
44,22
16,
38
PWR
Power Supply: +5 Volts.
VSS
1, 20
1, 22
2, 12
23,
34
6, 17
28,
40
GND
Ground: 0 Volts.
Table 3-2 : Pin Description Cont'd
Symbol
95C68/18
95C09
TYPE
Name and Function
PDIP
PLCC
TQFP
AFLG
ASTB
PAR
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