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參數(shù)資料
| 型號： | CA95C09-33CT |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 21/42頁 |
| 文件大?。?/td> | 180K |
| 代理商： | CA95C09-33CT |
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CA95C68/18/09
Tundra Semiconductor Corporation
3-52
Tundra Semiconductor Corporation
Input Register
The 64-bit, write-only Input Register is organized to appear
to the user as eight bytes of push-down storage. The number
of bytes stored in the register is monitored by a status circuit.
The register is considered full when eight bytes of data have
been loaded with the ECB or CBC ciphering algorithm in
use, or when one byte of data has been entered in either CFB
mode. It is considered empty when the data stored in it has
been or is being processed. The data in the register won't be
destroyed if the user attempts to write data into the Input
Register when it is full. Table 3-10 gives a summary of the
port ag associated with this register depending on the mode
of operation.
Output Register
The 64-bit, read-only Output Register is setup to appear to
the user as eight bytes of pop-up storage. A status circuit
detects the number of bytes stored in the Output Register.
The register is considered empty when all the data stored in it
has been read out by the host CPU, and is considered full if it
still contains one or more bytes of output data. If an attempt
is made to read data from the Output Register when it is
empty, the output buffers will remain in a tri-state condition.
Table 3-10 : Association of Master Port Flag
(
) and Slave Port Flag (
) with
Input and Output Registers
M,E,D Key Registers
There are three 64-bit, write-only key registers in the DCP;
the Master (M) Key Register, the Encrypt (E) Key Register,
and the Decrypt (D) Key Register. These registers are not
directly addressable, but can be loaded or read in response to
a command (See Command Descriptions). The Master key
can be loaded only with clear data through the Auxiliary
Port. The Encrypt and Decrypt Keys can be loaded as either
clear or cipher text through the Master or Auxiliary Port. If
the key data is encrypted, it is rst routed to the Input
Register where it is decrypted using the M Key, and then
written to the target key register from the Output Register.
Initialization Vector Registers
Two 64-bit registers are provided to store feedback from
Cipher Feedback and Cipher Block Chaining modes of
operation. One Initialization Vector (IVE) Register is used
during encryption, the other (IVD) during decryption. Both
registers can be loaded with either clear or encrypted data
through the Master Port. If encrypted data is loaded, it is rst
decrypted before being written into the corresponding IV
Register. Both registers may be read out through the Master
Port as either clear or encrypted text (see Command
Description Section).
Encrypt/
Decrypt
M4
Port Conguration
Input
Register
Flag
Output
Register
Flag
M3
M2
00
0
00
1
01
0
10
0
10
1
11
0
MFLG
SFLG
MFLG
SFLG
MFLG
SFLG
MFLG
SFLG
MFLG
SFLG
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