參數(shù)資料
型號(hào)： CDB5346
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 11/38頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR CS5346
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 24
采樣率（每秒）： 192k
數(shù)據(jù)接口： 串行
輸入范圍： 3.15 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 205mW @ 192kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： CS5346
已供物品： 板，纜線，CD
產(chǎn)品目錄頁(yè)面： 756 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： CS5346-CQZR-ND - IC ADC AUD 103DB 200KHZ 48-LQFP
598-1692-ND - IC ADC AUD 103DB 200KHZ 48LQFP
其它名稱： 598-1790
DS861PP3
19
CS5346
5. APPLICATIONS
5.1
Recommended Power-Up Sequence
1. Hold RST low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset
to its default settings.
2. Bring RST high. The device will remain in a low power state with the PDN bit set by default. The control
port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
5.2
System Clocking
The CS5346 will operate at sa mpling frequencies from 8 kHz to 200 kHz. This range is div ided into three
speed modes as shown in Table 1.
5.2.1
Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the
frequency at which audio samples for each channel are clocked out of the device. The FM bits (See “Func-
page 30.) configure the device to generate the proper clocks in Master Mode and receive the proper
clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and
LRCK frequencies.
Mode
Sampling Frequency
Single-Speed
8-50 kHz
Double-Speed
50-100 kHz
Quad-Speed
100-200 kHz
Table 1. Speed Modes
LRCK
(kHz)
MCLK (MHz)
* 64x
* 96x
128x
192x
256x
384x
512x
768x
1024x
32
-
---
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
-
---
11.2896
16.9344
22.5792
33.8680
45.1584
48
-
---
12.2880
18.4320
24.5760
36.8640
49.1520
64
-
8.1920
12.2880
16.3840
24.5760
32.7680
-
88.2
-
11.2896
16.9344
22.5792
33.8680
45.1584
-
96
-
12.2880
18.4320
24.5760
36.8640
49.1520
-
128
8.1920
12.2880
16.3840
24.5760
32.7680
-
176.4
11.2896
16.9344
22.5792
33.8680
45.1584
-
192
12.2880
18.4320
24.5760
36.8640
49.1520
-
Mode
QSM
DSM
SSM
* Only available in master mode.
Table 2. Common Clock Frequencies
相關(guān)PDF資料
PDF描述
CDB5345 EVALUATION BOARD FOR CS5345
ASM06DSEN-S243 CONN EDGECARD 12POS .156 EYELET
ASM06DSEH-S243 CONN EDGECARD 12POS .156 EYELET
MLG1005S82NJ INDUCTOR MULTILAYER 82NH 0402
CDB5341 BOARD EVAL FOR CS5341 STEREO ADC
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