參數(shù)資料
型號(hào): CDB5346
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 26/38頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR CS5346
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 2
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
輸入范圍: 3.15 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 205mW @ 192kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: CS5346
已供物品: 板,纜線,CD
產(chǎn)品目錄頁(yè)面: 756 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: CS5346-CQZR-ND - IC ADC AUD 103DB 200KHZ 48-LQFP
598-1692-ND - IC ADC AUD 103DB 200KHZ 48LQFP
其它名稱: 598-1790
32
DS861PP3
CS5346
7.8.2
Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 12.
7.9
Active Level Control - Address 0Ch
7.9.1
Active High/ Low (Bit 0)
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INTpin functions as an active low open drain driver and will require an exter-
nal pull-up resistor for proper operation.
7.10 Status - Address 0Dh
For all bits in this register, a ‘1’ means theassociated condition has occurred at least once since the register
was last read. A ‘0’ means the associated condition has NOT occurred since the last reading of the register.
Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register
defaults to 00h.
PGASoft
PGAZeroCross
Mode
0
Changes to affect immediately
0
1
Zero Cross enabled
1
0
Soft Ramp enabled
1
Soft Ramp and Zero Cross enabled (default)
Table 11. PGA Soft Cross or Zero Cross Mode Selection
Sel2
Sel1
Sel0
PGA/ADC Input
0
Microphone-Level Inputs (+32 dB Gain Enabled)
0
1
Line-Level Input Pair 1
0
1
0
Line-Level Input Pair 2
0
1
Line-Level Input Pair 3
1
0
Line-Level Input Pair 4
1
0
1
Line-Level Input Pair 5
1
0
Line-Level Input Pair 6
1
Reserved
Table 12. Analog Input Multiplexer Selection
76
543
21
0
Reserved
Active_H/L
76
543
21
0
Reserved
ClkErr
Reserved
Ovfl
Undrfl
相關(guān)PDF資料
PDF描述
CDB5345 EVALUATION BOARD FOR CS5345
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