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參數(shù)資料
| 型號(hào)： | CDB5361 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS5361 STEREO ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 198mW @ 5V |
| 工作溫度： | -10°C ~ 70°C |
| 已用 IC / 零件： | CS5361 |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 756 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS5361-KZZR-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP CS5361-KSZR-ND - IC ADC AUD 114DB 204KHZ 24-SOIC 598-1695-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP 598-1087-5-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP 598-1086-5-ND - IC ADC AUD 114DB 204KHZ 24-SOIC |
| 其它名稱： | 598-1547 |
CS5361
DS467F2
19
4.5
High-pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5361 may generate a small DC offset into the A/D con-
verter. The CS5361 includes a high-pass filter after the decimator to remove any DC offset which could result in re-
cording a DC level, possibly yielding “clicks” when switching between devices in a multichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the
HPF pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC offset
will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC
offset calibration by:
1) Running the CS5361 with the high-pass filter enabled until the filter settles. See the Digital Filter Character-
istics for filter settling time.
2) Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration
point and the CS5361.
4.6
Overflow Detection
The CS5361 includes overflow detection on both the left and right channels. This time multiplexed information is
presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a logical low as soon
as an overrange condition in either channel is detected. The data will remain low as specified in the Switching Char-
acteristics - Serial Audio Port section. This ensures sufficient time to detect an overrange condition regardless of the
speed mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has not been any
other overrange condition detected. Please note that an overrange condition on either channel will restart the time-
out period for both channels.
4.6.1
OVFL Output Timing
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S format, the OVFL
pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both cases the OVFL data
can be easily demultiplexed by using the LRCK to latch the data. In left-justified format, the rising edge of LRCK
would latch the right channel overflow status, and the falling edge of LRCK would latch the left channel overflow
status. In I2S format, the falling edge of LRCK would latch the right channel overflow status and the rising edge of
LRCK would latch the left channel overflow status.
4.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5361 requires careful attention to power supply and grounding arrange-
ments if its potential performance is to be realized. Figure 22 shows the recommended power arrangements, with
VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply
or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from
VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being
the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid un-
wanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 F, must be
positioned to minimize the electrical path from FILT+ and REFGND. The CDB5361 evaluation board demonstrates
the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only
to CMOS inputs.
4.8
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure
synchronous sampling, the MCLK and LRCK must be the same for all of the CS5361’s in the system. If only one
master clock source is needed, one solution is to place one CS5361 in Master mode, and slave all of the other
CS5361’s to the one master. If multiple master clock sources are needed, a possible solution would be to supply all
clocks from the same external source and time the CS5361 reset with the inactive edge of MCLK. This will ensure
that all converters begin sampling on the same clock edge.
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