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參數(shù)資料
| 型號： | CDB5361 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS5361 STEREO ADC |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 在以下條件下的電源（標準）： | 198mW @ 5V |
| 工作溫度： | -10°C ~ 70°C |
| 已用 IC / 零件： | CS5361 |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 756 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS5361-KZZR-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP CS5361-KSZR-ND - IC ADC AUD 114DB 204KHZ 24-SOIC 598-1695-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP 598-1087-5-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP 598-1086-5-ND - IC ADC AUD 114DB 204KHZ 24-SOIC |
| 其它名稱： | 598-1547 |
CS5361
16
DS467F2
4.0 APPLICATIONS
4.1
Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 204 kHz. The CS5361 must be set to the proper speed
mode via the mode pins, M1 and M0. Refer to Table 1.
4.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously gen-
erated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also
includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other
internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic
0.
4.2.1
Slave Mode
LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived from the mas-
ter clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master
clock and be equal to 64x Fs to maximize system performance. Refer to Table 2 for required clock ratios.
Table 2. CS5361 Slave Mode Clock Ratios
M1 (Pin 14)
M0 (Pin 13)
MODE
Output Sample Rate (Fs)
0
Single Speed Mode
2 kHz - 51 kHz
0
1
Double Speed Mode
50 kHz - 102 kHz
1
0
Quad Speed Mode
100 kHz - 204 kHz
11
Reserved
Table 1. CS5361 Mode Control
Single Speed Mode
Fs = 2 kHz to 51 kHz
Double Speed Mode
Fs = 50 kHz to 102 kHz
Quad Speed Mode
Fs = 100 kHz to 204 kHz
MCLK/LRCK Ratio
256x, 512x
128x, 256x
128x
SCLK/LRCK Ratio
32x, 64x, 128x
32x, 64x
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