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參數(shù)資料
| 型號： | CDB5361 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 6/23頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5361 STEREO ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 198mW @ 5V |
| 工作溫度： | -10°C ~ 70°C |
| 已用 IC / 零件： | CS5361 |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 756 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS5361-KZZR-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP CS5361-KSZR-ND - IC ADC AUD 114DB 204KHZ 24-SOIC 598-1695-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP 598-1087-5-ND - IC ADC AUD 114DB 204KHZ 24-TSSOP 598-1086-5-ND - IC ADC AUD 114DB 204KHZ 24-SOIC |
| 其它名稱： | 598-1547 |
CS5361
14
DS467F2
2.0 PIN DESCRIPTIONS
RST
124
FILT+
M/S
223
REFGND
LRCK
322
VQ
SCLK
421
AINR+
MCLK
520
AINR-
VD
619
VA
GND
718
GND
VL
817
AINL-
SDOUT
916
AINL+
MDIV
10
15
OVFL
HPF
11
14
M1
I2S/LJ
12
13
M0
Pin Name
#
Pin Description
RST
1
Reset (Input) - The device enters a low power mode when low.
M/S
2
Master/Slave Mode (Input) - Selects operation as either clock master or slave.
LRCK
3
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SCLK
4
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD
6
Digital Power (Input) - Positive power supply for the digital section.
GND
7,18 Ground (Input) - Ground reference. Must be connected to analog ground.
VL
8
Logic Power (Input) - Positive power for the digital input/output.
SDOUT
9
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
MDIV
10
MCLK Divider (Input) - Enables a master clock divide by two function.
HPF
11
High-pass Filter Enable (Input) - Enables the Digital High-Pass Filter.
I2S/LJ
12
Serial Audio Interface Format Select (Input) -Selects either the left-justified or I2S format for the SAI.
M0
M1
13,
14
Mode Selection (Input) - Determines the operational mode of the device.
OVFL
15
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
AINL+
AINL-
16,
17
Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
VA
19
Analog Power (Input) - Positive power supply for the analog section.
AINR-
AINR+
20,
21
Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
VQ
22
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
REF_GND
23
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
24
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
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