參數(shù)資料
型號(hào): CDB5364
廠商: Cirrus Logic Inc
文件頁數(shù): 15/42頁
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR CS5364
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: I²C,SPI?
在以下條件下的電源(標(biāo)準(zhǔn)): 365mW @ 192kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: CS5364
已供物品: 板,CD
相關(guān)產(chǎn)品: CS5364-CQZR-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP
598-1697-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP
598-1088-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP
22
DS625F4
CS5364
4.5
Serial Audio Interface (SAI) Format
The SAI port consists of two timing pins (SCLK, LRCK/FS) and four audio data output pins (SDOUT1/TDM,
SDOUT2, SDOUT3/TDM and SDOUT4). The CS5364 output is serial data in IS, Left-Justified (LJ), or Time
Division Multiplexed (TDM) digital audio interface formats. These formats are available to the user in both
Stand-Alone Mode and Control Port Mode.
4.5.1
IS and LJ Format
The IS and LJ formats are both two-channel protocols. During one LRCK period, two channels of data are
transmitted, odd channels first, then even. The MSB is always clocked out first.
In Slave Mode, the number of SCLK cycles per channel is fixed as described under “Serial Audio Interface
- IS/LJ Timing” on page 15. In Slave Mode, if more than 32 SCLK cycles per channel are received from a
master controller, the CS5364 will fill the longer frame with trailing zeros. If fewer than 24 SCLK cycles per
channel are received from a master, the CS5364 will truncate the serial data output to the number of SCLK
cycles received. For a complete overview of serial audio interface formats, please refer to Cirrus Logic Ap-
plication Note AN282.
Figure 10. IS Format
Figure 11. LJ Format
Odd Channels 1,3, ...
Even Channels 2,4, ...
LRCK
receiver latches data on rising edges of SCLK
SDOUT
SCLK
MSB
...
LSB
MSB
...
LSB
MSB
Odd Channels 1,3, ...
Even Channels 2,4, ...
LRCK
receiver latches data on rising edges of SCLK
MSB
...
LSB
MSB
...
LSB
SDOUT
SCLK
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