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參數(shù)資料
| 型號： | CDB5364 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR CS5364 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | I²C，SPI? |
| 在以下條件下的電源（標準）： | 365mW @ 192kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5364 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | CS5364-CQZR-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP 598-1697-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP 598-1088-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP |
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DS625F4
31
CS5364
4.13.2
IC Mode
In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should
be connected through a resistor to VLC or DGND, as desired. The state of the pins is latched when the
CS5364 is being released from RST.
A Start condition is defined as a falling transition of SDA while SCL is high. A Stop condition is a rising tran-
sition of SDA while SCL is high. All other transitions of SDA occur while SCL is low. The first byte sent to
the CS5364 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write). The upper five bits of the 7-bit address field are fixed at 10011. To communicate with a CS5364,
the chip address field, which is the first byte sent to the CS5364, should match 10011 and be followed by
the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP), which selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-incre-
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS5364 after each input byte is read and is input to the
CS5364 from the microcontroller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. The write
operation is aborted after the acknowledge for the MAP byte by sending a Stop condition. The following
pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Figure 17. IC Write Format
Figure 18. IC Read Format
4
5
6
7
24 25
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
1
0
1
1 AD1 AD0 0
SDA
INCR
6
5
4
3
2
1
0
7
6
1
0
7
6
1
0
7
6
1
0
1
2
3
8
9
12
16 17 18
19
10 11
13 14 15
27 28
26
DATA +n
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
1
0 0
1 1 AD1 AD0 0
SDA
1
0 0
1 1 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR
6
5
4
3 2 1 0
7
0
7
0
7
0
NO
16
8
9
12 13 14 15
4
5
6
7
0
1
20 21 22 23 24
26 27 28
2
3
10 11
17 18 19
25
ACK
DATA + n
STOP
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