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參數(shù)資料
| 型號(hào)： | CLC014AJE-TR13/NOPB |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 3/21頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CABLE EQUALIZER ADAPT 14-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 應(yīng)用： | 醫(yī)用型 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
| 配用： | SD901EVK-ND - BOARD EVAL CLC014, 016, 011, 006 SD014EVK-ND - BOARD EVALUATION CLC014 |
| 其它名稱： | *CLC014AJE-TR13 *CLC014AJE-TR13/NOPB CLC014AJE-TR13 |
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OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
DEVICE TESTING
Performance or compliancy testing of the CLC014 with Cable Clones is not allowed. Use of these devices is
contrary to the product's specifications and test procedures. Testing for product specifications or performance
using cable clones is invalid since cable clones have a different frequency response than the actual cable.
Testing with full length cable samples is recommended.
Input Interfacing
The CLC014 accepts either differential or single-ended input voltage specified in Static Performance. The
following sections show several suggestions for interfaces for the inputs and outputs of the CLC014.
SINGLE-ENDED INPUT INTERFACE: 75
Coaxial Cable
The input is connected single-ended to either DI or DI as shown in Figure 19. Balancing unused inputs helps to
lessen the effects of noise. Use the equivalent termination of 37.5
to balance the input impedance seen by
each pin. It also helps to terminate grounds at a common point. Resistors Rx and R y are recommended for
optimum performance. The equalizer inputs are self-biasing. Signals should be AC coupled to the inputs as
shown in Figure 19.
Figure 19. Single-Ended 75
Cable Input Interface
DIFFERENTIAL INPUT INTERFACE: Twisted Pair
A recommended differential input interface is shown in Figure 20. Proper voltage levels must be furnished to the
input pins and the proper cable terminating impedance must be provided. For Category 5 UTP this is
approximately 100
. Figure 20 shows a generalized network which may be used to receive data over a twisted
pair. Resistors R1 and R2 provide the proper terminating impedance and signal level adjustment. The blocking
capacitors provide AC coupling of the attenuated signal levels. The plots in TYPICAL PERFORMANCE
CHARACTERISTICS demonstrate various equalized data rates using Category 5 UTP at 100 meter lengths. A
full schematic of a recommended driver and receiver circuit for 100
Category 5 UTP is provided in Typical
(1)
Figure 20. Twisted Pair Input Interface
Copyright 1998–2013, Texas Instruments Incorporated
11
Product Folder Links: CLC014
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