參數(shù)資料
型號(hào)： CLC014AJE-TR13/NOPB
廠商： National Semiconductor
文件頁(yè)數(shù)： 6/21頁(yè)
文件大小： 0K
描述： IC CABLE EQUALIZER ADAPT 14-SOIC
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： 醫(yī)用型
電源電壓： 4.5 V ~ 5.5 V
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOICN
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
配用： SD901EVK-ND - BOARD EVAL CLC014, 016, 011, 006
SD014EVK-ND - BOARD EVALUATION CLC014
其它名稱： *CLC014AJE-TR13
*CLC014AJE-TR13/NOPB
CLC014AJE-TR13
OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
MINIMUM DATA TRANSITIONS
The CLC014 specifies a minimum transition rate. For the CLC014 this sets the minimum data rate for
transmitting data through any cable medium. The CLC014 minimum average transition density is found in the
POWER SUPPLY OPERATION AND THERMAL CONSIDERATIONS
The CLC014 operates from either +5V or
5.2V single supplies. Refer to Figure 17 when operating the part from
+5V. When operating with a
5.2V supply, the VEE pins should be bypassed to ground. The evaluation board and
associated literature provide for operation from either supply.
Maximum power dissipation occurs at minimum cable length. Under that condition, ICC = 58 mA.
Total power dissipated:
PT = (58 mA)(5V) = 290 mW
(3)
Power in the load:
PL = (0.7V)(11 mA) + (37.5)(11 mA)
2 = 12 mW
(4)
Maximum power dissipated on the die:
PDMAX = PT–PL = 278 mW
(5)
Junction Temperature =
(
θJA)(278 mW) + TA = T A + 26°C
(6)
Layout and Measurement
The printed circuit board layout for the CLC014 requires proper high-speed layout to achieve the performance
specifications found in the datasheet. The following list contains a few rules to follow:
1. Use a ground plane.
2. Decouple power pins with 0.1
μF capacitors placed ≤ 0.1” (3mm) from the power pins.
3. Design transmission strip lines from the CLC014's input and output pins to the board connectors.
4. Route outputs away from inputs.
5. Keep ground plane
≥ 0.025” (0.06mm) away from the input and output pads.
Figure 24 shows a block level measurement diagram, while Figure 31 on depicts a detailed schematic. A
pseudo-random pattern generator with low output jitter was used to provide a NRZI pattern to create the eye
Since most pattern generators have a 50
output impedance, a translation can be accomplished using a
CLC006 Cable Driver as an impedance transformer. A wide bandwidth oscilloscope is needed to observe the
high data rate eye pattern. When monitoring a single output that is terminated at both the equalizer output and
the oscilloscope, the effective output load is 37.5
. Consequently, the signal swing is half that observed for a
single-ended 75
termination.
14
Copyright 1998–2013, Texas Instruments Incorporated
Product Folder Links: CLC014
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