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參數(shù)資料
| 型號： | CLC014AJE-TR13/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 0K |
| 描述： | IC CABLE EQUALIZER ADAPT 14-SOIC |
| 標準包裝： | 2,500 |
| 應用： | 醫(yī)用型 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 14-SOICN |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
| 配用： | SD901EVK-ND - BOARD EVAL CLC014, 016, 011, 006 SD014EVK-ND - BOARD EVALUATION CLC014 |
| 其它名稱： | *CLC014AJE-TR13 *CLC014AJE-TR13/NOPB CLC014AJE-TR13 |
OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
Figure 24. Typical Measurement Block
Troubleshooting with scope probes can affect the equalization. For high data rates, use a low capacitance
probe with less than 2 pF probe capacitance. Evaluation boards and literature are available for quick prototyping
and evaluation of the CLC014 Adaptive Cable Equalizer. The CLC014 contains CMOS devices and operators
should use grounding straps when handling the parts.
Monolithic capacitor of about 0.1
μF placed less than 0.1” (3mm) from the pin
Tantalum capacitor of about 6.8
μF for large current signal swings placed as close as convenient to the
CLC014
Figure 25. Power Package Routing Fixture
To minimize ringing at the CLC014's inputs, place a 100
resistor in series with the input. This resistor reduces
inductance effects.
Several layout techniques can improve high speed performance:
Keep input, output and AEC traces well separated
Use balanced input termination's
Avoid routing traces close to the CLC014's input trace
Maintain common return points for components
Use guard traces
Copyright 1998–2013, Texas Instruments Incorporated
15
Product Folder Links: CLC014
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