參數(shù)資料
型號： CP82C50A-5Z
廠商： Intersil
文件頁數(shù)： 5/25頁
文件大小： 0K
描述： IC ASYNC COMM ELEMENT UART 40DIP
標準包裝： 9
特點： 單芯片 UART/BRG
通道數(shù)： 1，UART
規(guī)程： RS232C
電源電壓： 4.5 V ~ 5.5 V
帶并行端口： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
13
FN2958.5
August 24, 2006
82C50A
INTERRUPT ENABLE REGISTER (IER)
The Interrupt Enable Register (IER) is a Write register used
to independently enable the four 82C50A interrupts which
activate the interrupt (lNTRPT) output. All interrupts are
disabled by resetting IER(0) - IER(3) of the Interrupt Enable
Register. Interrupts are enabled by setting the appropriate
bits of the IER high. Disabling the interrupt system inhibits
the Interrupt Identification Register and the active (high)
INTRPT output. All other system functions operate in their
normal manner, including the setting of the Line Status and
Modem Status Registers. The contents of the Interrupt
Enable Register are indicated in Table 3 and are described
below.
IER(0): When programmed high (IER(0) = Logic 1), IER(0)
enables Received Data Available interrupt.
IER(1): When programmed high (IER(1) = Logic 1), IER(1)
enables the Transmitter Holding Register Empty interrupt.
IER(2): When Programmed high (IER(2) = Logic 1), IER(2)
enables the Receiver Line Status interrupt.
IER(3): When programmed high (IER(3) = Logic 1), IER(3)
enables the Modem Status interrupt.
IER(4) - IER(7): These four bits of the IER are logic 0.
FIGURE 1. 82C50A INTERRUPT CONTROL STRUCTURE
INTRPT
PIN 30
DR (LSR BIT 0)
ERBFI (IER BIT 0)
OE (LSR BIT 1)
PE (LSR BIT 2)
THRE (LSR BIT 5)
ETBEI (IER BIT 1)
FE (LSR BIT 3)
BI (LSR BIT 4)
ELSI (IER BIT 2)
DCTS (MSR BIT 0)
DDSR (MSR BIT 1)
TERI (MSR BIT 2)
DDCD (MSR BIT 3)
EDSSI (IER BIT 3)
TABLE 3. 82C50A ACCESSIBLE REGISTER SUMMARY
(NOTE: See Table 1 for how to access these registers.)
REGISTER
MNEMONIC
REGISTER BIT NUMBER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RBR
(Read Only)
Data Bit 7
(MSB)
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(LSB)
THR
(Write Only)
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
DLL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
IER
0
000
(EDSSI)
Enable
Modem
Status
Interrupt
(ELSI)
Enable
Receiver
Line
Status
Interrupt
(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ERBFI)
Enable
Received
Data
Available
Interrupt
IIR
(Read Only)
0
Interrupt ID
Bit (1)
Interrupt ID
Bit (0)
“0” 1F
Interrupt
Pending
LCR
(DLAB)
Divisor
Latch
Access
Bit
Set Break
Stick Parity
(EPS)
Even Parity
Select
(PEN)
Parity
Enable
(STB)
Number
of Stop
Bits
(WLSB1)
Word
Length
Select
Bit 1
(WLSB0)
Word
Length
Select
Bit 0
MCR
0
Loop
Out 2
Out 1
(RTS)
Request
to Send
(DTR)
Data
Terminal
Ready
LSR
0
(TEMT)
Transmitter
Empty
(THRE)
Transmitter
Holding
Register
Empty
(BI)
Break
Interrupt
(FE)
Framing
Error
(PE)
Parity
Error
(OE)
Overrun
Error
(DR)
Data
Ready
MSR
(DCD)
Data
Carrier
Detect
(RI)
Ring
Indicator
(DSR)
Data
Set
Ready
(CTS)
Clear
to
Send
(DDCD)
Delta
Data
Carrier
Detect
(TERI)
Trailing
Edge
Ring
Indicator
(DDSR)
Delta
Data
Set
Ready
(DCTS)
Delta
Clear
to
Send
SCR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSB, Data Bit 0 is the first bit transmitted or received.
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