參數(shù)資料
型號: CR16HCT9VJE7Y
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 101/157頁
文件大?。?/td> 1256K
代理商: CR16HCT9VJE7Y
101
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20.6.4
The transmission process can be started after the user has
loaded the buffer registers (data, ID, DLC, PRI) and set the
buffer status from TX_NOT_ACTIVE to TX_ONCE, TX_RTR
or TX_ONCE_RTR.
When the CPU writes TX_ONCE, the buffer will be
TX_BUSY as soon as CR16CAN has scheduled this buffer
for the next transmission. After the frame could be success-
fully transmitted, the buffer status will be automatically reset
to TX_NOT_ACTIVE when a data frame was transmitted or
to RX_READY when a remote frame was transmitted.
If
the
CPU
configures
TX_ONCE_RTR, it will transmit its data contents. During the
transmission the buffer state is 1111
2
as the CPU wrote 1110
2
into the status section of the CNSTAT register. After the suc-
cessful transmission the buffer enters the TX_RTR state and
waits for a remote frame. When it receives a remote frame, it
will go back into the TX_ONCE_RTR state, transmit its data
bytes and return to TX_RTR. If the CPU writes 1010
2
into the
buffer status section, it will only enter the TX_RTR state. But
it will not send its data bytes before it waits for a remote
frame. Figure 66 illustrates the possible transmit buffer
states.
TX Buffer States
the
message
buffer
to
write_buffer
TX_BUSYx
Y
(see text)
N
write
write ID/data
write
exit
Figure 65.
Buffer Write Routine
TX_ONCE
or
TX_ONCE_RTR
or
TX_RTR
TX_NOT_ACTIVE
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