參數(shù)資料
型號: CR16HCT9VJE7Y
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 59/157頁
文件大?。?/td> 1256K
代理商: CR16HCT9VJE7Y
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16.1.1
Each timer subsystem may be configured to generate two
fully independent PWM waveforms on the respective TIOx
pins. In this mode, the counter COUNTx is split and operates
as two independent 8-bit counters. Each counter increments
at the rate determined by the clock prescaler.
Each of the two 8-bit counters may be started and stopped
separately via the associated TxRUN bits. Once either of the
two 8-bit timers is running the clock prescaler starts counting.
Once the clock prescaler counter value matches the value of
the associated CxPRSC register field, COUNTx is incre-
mented.
Dual 8-bit PWM Mode
The period of the PWM output waveform is determined by
the value of the PERCAPx register. The TIOx output starts at
the default value as pro-grammed via the IOxCTL.PxPOL bit.
Once the counter value reaches the value of the period reg-
ister PERCAPx, the counter is reset to 00
16
upon the next
counter increment. Upon the following increment from 00
16
to 01
16
, the TIOx output will change to the opposite of the de-
fault value.
The duty cycle of the PWM output waveform is controlled by
the DTYCAPx register value. Once the counter value reach-
es the value of the duty cycle register DTYCAPx, the PWM
output TIOx changes back to its default value upon the next
counter increment. Figure 19 illustrates this concept.
The period time is determined by the following formula:
PWMperiod = (PERCAPx + 1) * (CxPRSC + 1) * T
CLK
The duty cycle in percent is calculated as follows:
DutyCycle[%] = (DTYCAPx / (PERCAPx+1)) *100
If the duty cycle register (DTYCAPx) holds a value which is
greater then the value held in the period register (PERCAPx)
the TIOx output will remain at the opposite of its default value
which corresponds to a duty cycle of 100%. If the duty cycle
register (DTYCAPx) register holds a value of 00
16
, the TIOx
output will remain at the default value which corresponds to
a duty cycle of 0%. In that case the value contained in the
PERCAPx register is irrelevant. This scheme allows the duty
cycle to be programmed in a range from 0% to 100%.
In order to allow fully synchronized updates of the period and
duty cycle compare values, the PERCAPx and DTYCAPx
registers are double buffered when operating in PWM mode.
Therefore if the user writes to either the period or duty cycle
register while either of the two PWM channels is enabled, the
new value will not take effect until the counter value matches
the previous period value or the timer is stopped.
Reading the PERCAPx or DTYCAPx register will always re-
turn the most recent value written to it.
The counter registers can be written if both 8-bit counters are
stopped. This allows the user to preset the counters before
starting and therefore generate PWM output waveforms with
a phase shift relative to one another. If the counter is written
with a value other then 00
16
it will start incrementing from that
value while TIOx remains at its default value until the first
00
16
to 01
16
transition of the counter value occurs. If the
counter is preset to values which are smaller or equal then
the value held in the period register (PERCAPx) the counter
will count up until a match between the counter value and the
PERCAPx register value occurs. The counter will then be re-
set to 00
16
and continue counting up. Alternatively the
counter may be written with a value which is greater then the
00
COUNTx
PERCAPx
DTYCAPx
TIOx (PxPOL=0)
TIOx (PxPOL=1)
TxRUN=1
01
00
01
02
03
04
05
06
07
08
09
0A
02
03
04
05
06
07
08
09
0A
Figure 19.
VTU PWM generation
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