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| 型號(hào)： | CR16HCT9VJE7Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 115/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT9VJE7Y |
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115
www.national.com
20.9.19 CAN Timer Register (CTMR)
The current value of the Time Stamp counter as described in
section 20.8 can be monitored via the CAN Timer Register.
15
CTMR[15:0]
0
r
The CAN Time register is a free running 16-bit counter. It
contains the number of CAN bits recognized by CR16CAN
since the register has been reset. The counter starts to incre-
ment from the value 0000
16
after a hardware reset. If the
Timer Stamp enable flag (TSTPEN) in the CAN global config-
uration register (CGCR) is set, the counter will also be reset
upon a message transfer of the message buffer 0.
As described in Time Stamp Counter on page 104, the con-
tents of CTMR are captured into the Time Stamp register of
the message buffer after successfully sending or receiving a
frame.
20.10
SYSTEM START-UP AND MULTI-INPUT
WAKE-UP
After system start-up, all CR16CAN related registers are in
their reset state. The CR16CAN module can be enabled after
all configuration registers are set to their desired value. The
following initial setting need to be made:
— configure the CAN Timing register (CTIM) See “Bit
Time Logic” on page 93.
— configure every buffer to its function as receive/trans-
mit Buffer Status/Control Register (CNSTAT) on page
105.
— set the acceptance filtering masks. See “Acceptance
Filtering” on page 95.
— enable the CR16CAN interface. See “CAN Global
Configuration Register (CGCR)” on page 108.
Before disabling the CR16CAN module, the user has to
make sure that no transmission is still pending.
Note:
The device can be awaken from a power saving mode
by an activity on the CAN bus by selecting the CAN RX pin
as an input to the Multi-Input Wake-Up module. In this case
the CR16CAN module must not be disabled before entering
the power saving mode. Disabling the CR16CAN module
also disables the CAN RX pin.
As an alternative, the CAN RX pin can be connected to any
other input pin of the Multi-Input Wake-Up module. This input
channel must then be configured to trigger a wake-up event
on a falling edge (if a dominant bit is represented by a low
level). In this case the CR16CAN module can be disabled be-
fore entering a power saving mode. After the device has
been waken up, the user has to manually enable the
CR16CAN again. All configuration and buffer registers still
contain the same data as prior to the power down phase.
20.10.1 External Connection
The CR16CAN uses two external pins, CANTX and CANRX
to connect to the physical layer of the CAN interface. They
provide the functionality as described in Table 38.
The logic levels are configurable by means of two control
flags CTX and CRX of the Global Configuration Register
CGCR (see “CAN Global Configuration Register (CGCR)” on
page 108.
20.10.2 Transceiver Connection
An external Transceiver Chip needs to be connected be-
tween the CAN block and the bus. It is used to establish a
bus connection in differential mode and furthermore provides
the driver and protection requirements.
Figure 72 shows a possible ISO-High-Speed configuration
.
20.10.3 Timing Requirements
Processing messages and updating message buffers require
a certain number of clock cycles by CR16CAN as shown in
Table 39. These requirements may lead to some restrictions
regarding the Bit Time Logic settings and the overall
CR16CAN performance which are described below in more
detail.
Table 39
CR16CAN Internal Timing
0
Table 38
External CR16CAN Pins
Signal Name
Type
Description
CANTX
Output
Transmit data to the CAN bus
CANRX
Input
Receive data from the CAN bus
task
# cycles
a
a. Wait cycles need to be added for CPU access to the
object memory as described in CPU Access to
CR16CAN Registers/Memory on page 104.
occurrence/
frame
b
b. Depends on the number of matching identifiers.
copy hidden buffer to receive
message buffer
update status from TX_RTR
to TX_ONCE_RTR
schedule a message for trans-
mission
17
0-1
3
0-15
2
0-1
VCC
to other modules
termination
CAN Bus Line
120
120
VCC
RS GND
8
BUS_L
BUS_H
TX
RX
REF
Transceiver Chip
GND
3
7
6
2
5
4
1
GND
CANTX
CANRX
CR16CAN
CORE BUS
Figure 72.
External Transceiver Connection
(ISO-High-Speed)
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| CR16HCT9VJE8 | Microcontroller |
| CR16HCT9VJE8Y | Microcontroller |
| CR16HCT9VJE9 | Microcontroller |
| CR16HCT9VJE9Y | Microcontroller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CR16HCT9VJE8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJEX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
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