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| 型號(hào)： | CR16HCT9VJE7Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 104/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT9VJE7Y |
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104
20.7.2
The interrupt code IST[3:0] can be used within the interrupt
handler as a displacement in order to jump to the relevant
subroutine.
The CAN Interrupt Code Enable (CICEN) register is used in
the CAN interrupt handler if the user wants to service all re-
ceive buffer interrupts first followed by all transmit buffer in-
terrupts. In this case, the user can first enable only all receive
buffer interrupts to be coded, scan and service all pending in-
terrupt requests in the order of their priority. Then, the user
changes the CICEN register to disable all receive buffers, but
enable all transmit buffers and service all pending transmit
buffer interrupt requests according to their priorities.
Usage Hints
20.8
CR16CAN features a free running 16-bit timer (CTMR) incre-
menting every bit time recognized on the CAN bus. The value
of this timer during the ACK slot is captured into the TSTP
register of a message buffer after a successful transmission
or reception of a message. Figure 68 shows a simplified
block diagram of the Time Stamp counter.
TIME STAMP COUNTER
The timer can be synchronized over the CAN network by re-
ceiving or transmitting a message to/from buffer 0. In that
case the TSTP register of buffer 0 captures the current
CTMR value during the ACK slot of a message (as above)
and afterwards the CTMR is reset to 0000
2
. Synchronization
can be enabled or disabled via the CGCR.TSTPEN bit.
20.9
CR16CAN occupies 144 words in the memory address
space. This space is separated into 15*8 + 8(reserved) words
for the message buffers and 14 + 2(reserved) words for con-
trol and status.
MEMORY ORGANIZATION
20.9.1
All memory locations occupied by the message buffers are
shared by the CPU and CR16CAN (dual ported RAM). The
CR16CAN and the CPU normally have single cycle access to
this memory. However, if an access contention occurs, the
access to the memory is altered every cycle until the conten-
tion is resolved. This internal access arbitration is transparent
to the user.
Both word and byte access to the buffer RAM are allowed. If
a buffer is busy during the reception of an object (copy pro-
cess from the hidden receive buffer) or is scheduled for trans-
mission, the CPU has no write access to the data contents of
the buffer. Write to the status/control byte and read access to
the whole buffer is always enabled.
All configuration and status registers can either be accessed
by CR16CAN or the CPU only. These registers provide single
cycle word and byte access without any potential wait state.
All register descriptions within the next sections utilize the fol-
lowing layout:
bit
15
... bit name ...
... reset value ...
... CPU access ...
r = register bit is read only
w = register bit is write only
r/w = register bit is read/write
CPU Access to CR16CAN Registers/Memory
20.9.2
The message buffers are the communication interfaces be-
tween CAN and the CPU for the transmission and the recep-
tion of CAN frames. There are 15 message buffers located at
fixed addresses in the RAM location. As shown in Table 25,
each buffer consists of two words reserved for the identifiers,
4 words reserved for up to eight CAN data bytes, one word is
reserved for time stamp and one word for data length code,
transmit priority code and the buffer status code.
Message Buffer Organization
16-bit counter
TSTP register
CAN bits on the bus
ACK slot & buffer 0 active
ACK slot
+1
Reset
Figure 68.
Time Stamp Counter
... bit number ...
bit
0
Table 25
Message Buffer Organization
ADDR
BUFFER
register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
xxxE
16
ID1
XI28
ID10
XI27
ID9
XI26
ID8
XI25
ID7
XI24
ID6
XI23
ID5
XI22
ID4
XI21
ID3
XI20
ID2
XI19
ID1
XI18
ID0
SRR
RTR
XI3
IDE
XI17
XI16
XI15
xxxC
16
ID0
XI14
XI13
XI12
XI11
XI10
XI9
XI8
XI7
XI6
XI5
XI4
XI2
XI1
XI0
RTR
xxxA
16
DATA0
Data
1.7
Data
Data
1.6
Data
Data
1.5
Data
Data
1.4
Data
Data
1.3
Data
Data
1.2
Data
Data
1.1
Data
Data
1.0
Data
Data
2.7
Data
Data
2.6
Data
Data
2.5
Data
Data
2.4
Data
Data
2.3
Data
Data
2.2
Data
Data
2.1
Data
Data
2.0
Data
xxx8
16
DATA1
3.7
Data
3.6
Data
3.5
Data
3.4
Data
3.3
Data
3.2
Data
3.1
Data
3.0
Data
4.7
Data
4.6
Data
4.5
Data
4.4
Data
4.3
Data
4.2
Data
4.1
Data
4.0
Data
xxx6
16
DATA2
5.7
Data
5.6
Data
5.5
Data
5.4
Data
5.3
Data
5.2
Data
5.1
Data
5.0
Data
6.7
Data
6.6
Data
6.5
Data
6.4
Data
6.3
Data
6.2
Data
6.1
Data
6.0
Data
xxx4
16
DATA3
7.7
7.6
7.5
7.4
7.3
7.2
7.1
TSTP
9
7.0
TSTP
8
8.7
TSTP
7
8.6
TSTP
6
8.5
TSTP
5
8.4
TSTP
4
8.3
TSTP
3
8.2
TSTP
2
8.1
TSTP
1
8.0
TSTP
0
xxx2
16
TSTP
TSTP15
TSTP14
TSTP13
TSTP12
TSTP11
TSTP10
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| CR16HCT9VJE8 | Microcontroller |
| CR16HCT9VJE8Y | Microcontroller |
| CR16HCT9VJE9 | Microcontroller |
| CR16HCT9VJE9Y | Microcontroller |
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| CR16HCT9VJE8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJEX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
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