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| 型號(hào)： | CR16HCT9VJE8 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 36/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT9VJE8 |
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36
11.0
Power Management
The Power Management Module (PMM) improves the effi-
ciency of the device by changing the operating mode (and
therefore the power consumption) according to the required
level of device activity.
The device can operate in any of four power modes:
— Active
— Power Save
— Idle
— Halt
Table 12 summarizes the main properties of the four operat-
ing modes: the state of the high-frequency oscillator (on or
off), the type of clock used by most modules, and the clock
used by the Timing and Watchdog Module (TWM).
Table 12
Power Mode Operating Summary
The low-frequency oscillator continues to operate in all four
modes and power must be provided continuously to the de-
vice power supply pins. In the Halt mode, however, the inter-
nal SLCLK does not toggle, and as a result, the TWM timer
and Watchdog Module do not operate. For the Power Save
and Idle modes, the high-frequency oscillator can be turned
on or off under software control, as long as the low-frequency
oscillator is used.
11.1
In the Active mode, all device modules are fully operational.
This is the operating mode upon reset. Most device modules
use the clock generated by the high-frequency clock oscilla-
tor. The clock rate is determined by the external crystal net-
work.
Power consumption in the Active mode can be reduced by
selectively disabling unused modules and/or by executing
the WAIT instruction. When WAIT is executed, the core stops
executing new instructions and waits for an interrupt.
ACTIVE MODE
11.2
In the Power Save mode, all device modules operate off the
low-frequency clock. If the low-frequency clock is generated
from an external crystal network, the high-frequency clock
oscillator can be turned off to further reduce power consump-
tion.
All on-chip modules continue to operate in the Power Save
mode, with the SLCLK acting as their system clock. If this
mode is entered by using the WAIT command, the CPU is in-
active and waits for an interrupt to wake up. Otherwise, CPU
continues to function normally at the lower frequency of the
slow clock.
The low frequency of the clock in Power Save mode limits the
operation of modules such as the USARTs, MICROWIRE in-
terface, A/D Converter, and timers because they are driven
POWER SAVE MODE
by the slow clock rather than the normal high-speed clock. In
order to work properly in Power Save mode, modules that
perform real-time operations (such as a USART baud rate
generator) must be reprogrammed to use the slower clock.
To reduce power consumption as much as possible, the pro-
gram should execute a WAIT instruction during periods of
CPU inactivity.
11.3
In the Idle mode, the clock is stopped for most of the device.
Only the Power Management Module and Timing and Watch-
dog Module continue to operate. Both of these modules use
the slow clock in this mode.
IDLE MODE
11.4
In the Halt mode, all device clocks are disabled and the high-
frequency oscillator is shut off. In this mode, the device con-
sumes the least possible power while maintaining the device
memory and register contents. The low-frequency oscillator
continues to operate in this mode, but with very low power
consumption due to its power-optimized design.
HALT MODE
11.5
CLOCK INPUTS AND RESET
CONFIGURATION
The system uses a high frequency clock Active mode. The
source of this clock in the device is a high frequency crystal
oscillator. The Oscillating High Frequency Clock (OHFC) in-
put indicates to the Power Management Module (PMM)
when this clock is stable and therefore usable. The clock can
be used when OHFC is set to 1. The PMM does not use the
high frequency clock when OHFC is set to 0. OHFC can be
the output of a clock monitor or a strapped input signal to this
module.
The low frequency clock is used in Power Save mode as the
system clock source. In Idle mode, it is used as the clock
source for the PMM and the TWM, both of which remain
clocked. The clock source may be a low frequency clock os-
cillator or the prescaler from the high frequency clock.
The Oscillating Low Frequency Clock (OLFC) input indicates
to the PMM when the clock is stable and therefore usable.
When OLFC is set to 1, it indicates that the clock can be
used. When OLFC is set to 0, the PMM does not use the low
frequency clock. OLFC is generated by the “slow clock good”
output of the Dual Clock and Reset module (CLK2RES).
While in reset (i.e., the reset signal is active), the PMM out-
puts the clock as long as the clock selected for use upon re-
set is stable (OHFC or OLFC are 1). If the clock selected is
not stable, the PMM clock output remains low.
11.6
Switching from a higher to a lower power consumption mode
is accomplished by writing an appropriate value to the Power
Management Control/Status Register (PMCSR). Switching
from a lower power consumption mode to the Active mode is
usually triggered by a hardware interrupt. Figure 6 shows the
four power consumption modes and the events that trigger a
transition from one mode to another.
Some of the power-up transitions are based on the occur-
rence of a wake-up event. An event of this type can be either
SWITCHING BETWEEN POWER MODES
Mode
High-Frequency
Oscillator
Clock Used TWM Clock
Active
Power Save On or Off
Idle
Halt
On
Main Clock
Slow Clock
None
None
Slow Clock
Slow Clock
Slow Clock
None
On or Off
Off
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相關(guān)代理商/技術(shù)參數(shù) |
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| CR16HCT9VJE8Y | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller |
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| CR16HCT9VJEXY | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
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