參數(shù)資料
型號(hào)： CR16MCS9VJE8Y
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 117/157頁
文件大小： 1256K
代理商： CR16MCS9VJE8Y
117
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21.0
Analog Comparators
The Dual Analog Comparator (ACMP2) module contains two
independent analog comparators with all necessary control
logic. Each comparator unit compares the analog input volt-
ages applied to two input pins and determines which voltage
is higher. The comparison results can be placed on two out-
put pins and/or read by the software from a register.
Figure 73 is a block diagram of the Dual Analog Comparator
module.
The two comparators are designated Comparator 1 (CMP1)
and Comparator 2 (CMP2). Each comparator has a positive
and a negative input, called CMP1P and CMP1N for Com-
parator 1 and CMP2P and CMP2N for Comparator 2. An op-
tional output, CMP1O for Comparator 1 or CMP2O for
Comparator 2, allows the external hardware to read the com-
parison results. If the positive input is greater than the nega-
tive input, the result is a logic 1. Otherwise, the result is a
logic 0. These same results are available to the software by
reading the CMPCTRL register. CMP1OP and CMP2OP are
the direct outputs of the analog comparator. These signals
are connected to the channels of the Multi-Wake-Up module.
21.1
ANALOG COMPARATOR CONTROL/
STATUS REGISTER (CMPCTRL)
The CMPCTRL register is a byte-wide, read/write register
that controls the comparator module and contains the com-
parison results. The control bits are read/write bits and the re-
sult bits are read-only bits. This register is cleared upon
reset. The register format is shown below.
CMP1RD
Comparator 1 Read. This read-only bit con-
tains the output of Comparator 1 when the
comparator
is
enabled
CMP1RD is set to 1 when the voltage on
CMP1P is greater than the voltage on CMP1N.
This bit is always 0 when Comparator 1 is dis-
abled.
Comparator 2 Read. This read-only bit con-
tains the output of Comparator 2 when the
comparator
is
enabled
CMP2RD is set to 1 when the voltage on
CMP2P is greater than the voltage on CMP2N.
This bit is always 0 when Comparator 2 is dis-
abled.
Comparator 1 Enable. This read/write bit en-
ables (1) or disables (0) Comparator 1.
Comparator 2 Enable. This read/write bit en-
ables (1) or disables (0) Comparator 2.
Comparator 1 Output Enable. This read/write
bit, when set to 1, enables the use of the
CMP1O pin as the output of Comparator 1
when Comparator 1 is enabled (CMP1EN=1).
If Comparator 1 is disabled (CMP1EN=0), set-
ting the CMP1OE bit results in a logic 0 on the
CMP1O output pin.
Comparator 2 Output Enable. This read/write
bit, when set to 1, enables the use of the
CMP2O pin as the output of Comparator 2
(CMP1EN=1).
CMP2RD
(CMP2EN=1).
CMP1EN
CMP2EN
CMP1OE
CMP2OE
when Comparator 2 is enabled (CMP2EN=1).
If Comparator 2 is disabled (CMP2EN=0), set-
ting the CMP2OE bit results in a logic 0 on the
CMP2O output pin.
21.2
The comparator I/O pins are alternate functions of the Port L
pins. In order for a comparator to operate, its two input pins
must be configured to operate as inputs in the alternate func-
tion mode.
Using a comparator's output pin is optional. If it is to be used,
it must be configured to operate as an output in the alternate
function mode. The comparison result bits in the CMPCTRL
register are available to the CPU whether or not the output
pin is enabled.
The comparators uses DC current whenever they are en-
abled. Therefore, in order to reduce power consumption, it is
recommended that the comparators be disabled when they
are not needed, especially before entering any of the Power
Save modes.
ANALOG COMPARATOR USAGE
7
6
5
4
3
2
1
0
Reserved CMP2OE CMP1OE CMP2EN CMP1EN CMP2RD CMP1RD
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