參數(shù)資料
型號: CR16MCS9VJE8Y
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 64/157頁
文件大小: 1256K
代理商: CR16MCS9VJE8Y
www.national.com
64
ing the register will return the current value of the counter.
The register may only be written if the counter is stopped i.e.
if both TxRUN bits associated with a timer subsystem are
cleared. The registers are cleared upon reset (0000).
15
CNTx
16.2.9
The Period/Capture (PERCAPx) registers are word-wide
read/write registers. There are a total of four registers called
PERCAP1 through PERCAP4, one for each timer sub-
system. The register hold the period compare value in PWM
mode of the counter value at the time the last associated cap-
ture event occurred. In PWM mode the register is double
buffered. If a new period compare value is written while the
counter is running, the write will not take effect until counter
value matches the previous period compare value or until the
counter is stopped. Reading may take place at any time and
will return the most recent value which was written. The PER-
CAPx registers are reset to 0000 upon reset.
15
PCAPx
Period/Capture Registers (PERCAPx)
16.2.10 Duty Cycle / Capture Registers (DTYCAPx)
The Duty Cycle/Capture (DTYCAPx) registers are word-wide
read/write registers. There are a total of four registers called
DTYCAP1 through DTYCAP4, one for each timer sub-
system. The registers hold the period compare value in PWM
mode or the counter value at the time the last associated
capture event occurred. In PWM mode the register is double
buffered. If a new duty cycle compare value is written while
the counter is running, the write will not take effect until the
counter value matches the previous period compare value or
until the counter is stopped. In other words, the update takes
effect on period boundaries only. Reading may take place at
any time and will return the most recent value which was writ-
ten. The DTYCAPx registers are reset to 0000
16
upon reset
.
15
DCAPx
0
0
0
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