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| 型號： | CR16MCS9VJE8Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 93/157頁 |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16MCS9VJE8Y |
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Special error handling for the TEC counter is performed in
the following situations:
— A stuff error occurs during arbitration, when a transmit-
ted ‘recessive’ stuff bit is received as a ‘dominant’ bit.
This does not lead to an increment of the TEC.
— An ACK-error occurs in an error passive device and no
‘dominant’ bits are detected while sending the passive
error flag. This does not lead to an increment of the
TEC.
— If only one device is on the bus and this device trans-
mits a message, it will get no acknowledgment. This
will be detected as an error and the message will be re-
peated. When the device goes ‘error passive’ and de-
tects an acknowledge error, the TEC counter is not
incremented. Therefore the device will not go from ‘er-
ror passive’ to the ‘bus off’ state due to such a condi-
tion.
20.2.3
In the Bit Time Logic (BTL), the CAN bus speed and the Syn-
chronization Jump Width can be configured by the user.
CR16CAN divides a nominal bit time into three time seg-
ments: synchronization segment, time segment 1 (TSEG1)
and time segment 2 (TSEG2). Figure 52 shows the various
elements of a CAN bit time.
Bit Time Logic
CAN Bit Time
The number of time quanta in a CAN bit (CAN Bit Time) lies
between 4 and 25. The sample point is positioned between
TSEG1 and TSEG2 and the transmission point is positioned
at the end of TSEG2.
The
time segment 1
includes the propagation segment and
the phase segment 1 as specified in the CAN specification
2.0.B. The length of the time segment 1 in time quantas (tq)
is defined by the TSEG1[3:0] bits.
The
time segment 2
represents the phase segment 2 as
specified in the CAN specification 2.0.B. The length of the
time segment 2 in time quantas (tq) is defined by the
TSEG2[3:0] bits.
The
Synchronization Jump Width
(SJW) defines the max-
imum number of time quanta (tq) by which a received CAN
bit can be shortened or lengthened in order to achieve re-
synchronization on ‘recessive’ to ‘dominant’ data transitions
on the bus. In the CR16CAN implementation the SJW has to
be configured less or equal to TSEG1 or TSEG2, whatever is
smaller.
Synchronization
A CAN device expects the transition of the data signal to be
within the synchronization segment of each CAN bit time.
This segment has the fixed length of one time quantum.
However, two CAN nodes never operate at exactly the same
clock rate and furthermore the bus signal may deviate from
the ideal waveform due to the physical conditions of the net-
work (bus length and load). In order to compensate for the
various delays within a network, the sample point can be po-
sitioned by programming the length of time segments 1 and
2 (see Figure 52).
In addition to that, two types of synchronization are support-
ed. The BTL logic compares the incoming edge of a CAN bit
with the internal bit timing. The internal bit timing can be
adapted by either hard or soft synchronization (re-synchroni-
zation).
Hard synchronization
is done at the beginning of a new
frame with the falling edge on the bus while the bus is idle.
This is interpreted as the SOF. It restarts the internal logic.
Soft synchronization
is used during the reception of a bit
stream to lengthen or shorten the internal bit time. Depend-
ing on the phase error (e), the time segment 1 may be in-
creased or the time segment 2 may be decreased by a
specific value, the re-synchronization jump width (SJW).
The phase error is given by the deviation of the edge to the
SYNC segment, measured in CAN clocks. The value of the
phase error is defined as:
e = 0, if the edge occurs within the SYNC segment.
e > 0, if the edge occurs within TSEG1
e < 0, if the edge occurs within TSEG2 of the previous bit.
ONE TIME QUANTUM
INTERNAL
TIME QUANTA
CLOCK
A
TIME SEGMENT 1 (TSEG1)
TIME SEGMENT 2 (TSEG2)
1 tq
2 to 16 tq
1 to 8 tq
SAMPLE
POINT
A = synchronization segment (Sync)
Figure 52.
Bit Timing
4 to 25 tq
TRANSMISSION
POINT
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CR16MCS9VJE9 | 功能描述:16位微控制器 - MCU RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| CR16MCS9VJE9/NOPB | 功能描述:16位微控制器 - MCU RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| CR16MCS9VJE90 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16MCS9VJE91 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16MCS9VJE92 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
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