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型號(hào): CR16MCT5VJE7Y
英文描述: Microcontroller
中文描述: 微控制器
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代理商: CR16MCT5VJE7Y
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20.9.9
The Can Timing Register (CTIM) defines the configuration of
the Bit Time Logic (BTL).
15
9
8
7
PSC[6:0]
SJW[1:0] TSEG1[3:0]
0
r/w
CAN Timing Register (CTIM)
PSC[6:0]
Prescaler Configuration. These bits set the
CAN prescaler. The settings are shown in
Table 31
SJW[1:0]
Synchronization Jump Width. These bits set
the Synchronization Jump Width which can be
programmed between 1 and 4 time quanta
(see Table 32).
Note:
The settings of SJW has to be configured to be small-
er or equal to TSEG1 and TSEG2
TSEG1[3:0] Time Segment 1. These bits configure the
length of the Time Segment 1 (TSEG1). It is not
recommended to configure the time segment 1
to be smaller than 2tq. (see Table 33).
TSEG2[2:0] Time Segment 2. The TSEG2[2:0] bits set the
number of time quanta (tq) for phase segment
2 (see Table 34).
20.9.10 Global Mask Registers (GMSK — GMSKB and
GMSKX)
The GMSKB and GMSKX registers allow you to globally
mask, or “don’t care” the incoming extended/standard identi-
fier bits, RTR/XRTR and IDE. Throughout this document, the
GMSKB and GMSKX 16-bit registers are referenced as a 32-
bit register GMSK.
6
3
2
0
TSEG2[2:0]
Table 31
CAN Prescaler Settings
PS
C6
PS
C5
PS
C4
PS
C3
PS
C2
PS
C1
PS
C0
CAN
prescaler
(PSC)
0
0
0
0
0
0
0
2
0
0
0
0
0
0
1
3
0
0
0
0
0
1
0
4
0
0
0
0
0
1
1
5
0
0
0
0
1
0
0
6
:
:
:
:
:
:
:
1
1
1
1
1
0
1
127
1
1
1
1
1
1
0/1
128
Table 32
SJW Settings
SJW1
SJW0
Synchronization Jump Width
(SJW)
0
0
1 tq
0
1
2 tq
1
0
3 tq
1
1
4 tq
Table 33
Time Segment 1 Settings
TSEG
13
TSEG
12
TSEG
11
TSEG
10
Length of Time
(TSEG1)
0
0
0
0
not recommended
0
0
0
1
2 tq
0
0
1
0
3 tq
0
0
1
1
4 tq
0
1
0
0
5 tq
0
1
0
1
6 tq
0
1
1
0
7 tq
0
1
1
1
8 tq
1
0
0
0
9 tq
1
0
0
1
10 tq
1
0
1
0
11 tq
1
0
1
1
12 tq
1
1
0
0
13 tq
1
1
0
1
14 tq
1
1
1
0
15 tq
1
1
1
1
16 tq
Table 34
Time Segment 2 Settings
TSEG22
TSEG21
TSEG20
Length of
TSEG2
0
0
0
1 tq
0
0
1
2 tq
0
1
0
3 tq
0
1
1
4 tq
1
0
0
5 tq
1
0
1
6 tq
1
1
0
7 tq
1
1
1
8 tq
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