參數(shù)資料
型號(hào)： CR16MCT5VJE7Y
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 69/157頁
文件大小： 1256K
代理商： CR16MCT5VJE7Y
69
www.national.com
17.5.2
Upon reset, all non-reserved bits are cleared to 0. The regis-
ter format is shown below.
15 9
8
7
6
5
MCD
V
[6:0]
MICROWIRE Control Register (MWCTL)
MEN
MICROWIRE Enable. This bit enables (1) or
disables (0) the MICROWIRE interface mod-
ule. Clearing this bit disables the module,
clears the status bits in the MICROWIRE status
register (the MBSY, MRBF, and MOVR flags in
MWSTAT), and places the MICROWIRE inter-
face pins in the states described in Table 18.
Table 18
Pin Values with MICROWIRE
Disabled
MMNS
MICROWIRE Master/Slave Select. When
cleared to 0, the device operates as a slave.
When set to 1, the device operates as the mas-
ter.
MICROWIRE Mode Select (8- or 16-bit). When
set to 0, the device operates in 8-bit mode.
When set to 1, the device operates in 16-bit
mode. This bit should only be changed when
MMOD
the module is disabled or the MICROWIRE in-
terface is idle (MWSTAT.MBSY=0).
MICROWIRE Echo Back. This bit enables (1)
or disables (0) the echo back function in slave
mode. This bit should be written only when the
MICROWIRE interface is idle (MWSTAT.MB-
SY=0). The MECH bit is ignored in master
mode. The MWDAT register is valid from the
time the register has been written until the end
of the transfer.
In the echo back mode, MDODI is transmitted
(echoed back) on MDIDO if MWDAT does not
contain any valid data. With the echo back
function disabled, the data held in the MWDAT
register is transmitted on MDIDO, whether or
not the data is valid.
MICROWIRE Enable Interrupt on Overrun.
This bit enables or disables the overrun error
interrupt. When set to 1, an interrupt is gener-
ated when the Receive Overrun Error flag
(MWSTAT.MOVR) is set. Otherwise, no inter-
rupt is generated when an overrun error oc-
curs. This bit should only be enabled in master
mode.
MICROWIRE Enable Interrupt for Read. When
set to 1, an interrupt is generated when the
Read Buffer Full flag (MWSTAT.MRBF) is set.
Otherwise, no interrupt is generated when the
read buffer is full.
MICROWIRE Enable Interrupt for Write. When
set to 1, an interrupt is generated when the
Busy bit (MWSTAT.MBSY) is cleared, which in-
dicates that a data transfer sequence has been
completed and the read buffer is ready to re-
ceive the new data. Otherwise, no interrupt is
generated when the Busy bit is cleared.
MECH
MEIO
MEIR
MEIW
Figure 31.
MWDAT Register Structure
Shift Register
Read Buffer
Low-Byte
High-Byte
write
(store)
1
0
MWMOD
DOUT
DIN
read
(store & MWMOD)
Low-Byte
High-Byte
MWDAT
4
3
2
1
0
MID
L
MSK
M
MEI
W
MEI
R
MEI
O
MEC
H
MMO
D
MMN
S
ME
N
MSK
Master: MnIDL Bit
Slave: input
Input
Master: input
Slave: TRI-STATE
Master: known Value
Slave: input
MCS
MDIDO
MDODI
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