- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366891 > CR16MCT5VJE7Y Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | CR16MCT5VJE7Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 31/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16MCT5VJE7Y |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)當(dāng)前第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
31
www.national.com
10.0
Interrupts
The Interrupt Control Unit (ICU31L) receives interrupt re-
quests from internal and external sources and generates in-
terrupts to the CPU. Interrupts from the timers, USARTs,
MICROWIRE/SPI interface, Multi-Input Wake-Up, and A/D
converter are all maskable interrupts. The highest-priority in-
terrupt is the Non-Maskable Interrupt (NMI), which is trig-
gered by a falling edge received on the NMI input pin. The
NMI pin is not available on the 44-pin packages.
10.1
An
exception
is an event that temporarily stops the normal
flow of program execution and causes execution of a sepa-
rate service routine. Upon completion of the service routine,
execution of the interrupted program continues from the point
at which it was stopped.
There are two kinds of exceptions, called
traps
and
inter-
rupts
. A trap is the result of some action or condition in the
program itself, such as execution of an Exception (EXCP) in-
struction. An interrupt is a CPU-external event, such as a sig-
nal received on a Multi-Input Wake-Up input or a request
from an on-chip peripheral module for service.
The operation of traps is beyond the scope of this data sheet.
For information on traps, and for additional detailed informa-
tion on interrupts not provided in this data sheet, please refer
to the CompactRISC CR16B Programmer's Reference Man-
ual.
INTERRUPT OPERATION
10.1.1
When an interrupt occurs, the on-chip hardware performs the
following steps:
1. Decrements the Interrupt Stack Point (ISP) by four.
2. Saves the contents of the Program Counter (PC) and
Processor Status Register (PSR) on the interrupt stack.
3. Clears the I, P, and T bits in the Processor Status Regis-
ter (PSR). These are the Global Maskable Interrupt En-
able bit, Trace Trap Pending bit, and Trace bit,
respectively.
4. Reads the interrupt vector from the Interrupt Vector Reg-
ister (IVCT).
5. Combines the interrupt vector with the value in the Inter-
rupt Base (INTBASE) register to obtain an address in
the Interrupt Dispatch Table, and loads the dispatch ta-
ble entry into the Program Counter (PC).
From this point onward, the CPU executes the interrupt ser-
vice routine. The service routine ends with a Return from Ex-
ception (RETX) instruction. This returns the CPU to the
interrupted program. The CPU restores the contents of the
PC and PSR registers from the stack and increments the In-
terrupt Stack Pointer by four.
Interrupt Operation Summary
10.1.2
When an interrupt or trap occurs, the CPU executes a ser-
vice routine. There are different service routines for different
interrupts and traps. Each service routine may reside any-
where in program memory. The starting addresses of the ser-
vice routines are contained in a table called the Dispatch
Table. Entries in the table are organized in the order shown
in Table 10.
Service Routine Addresses
Table 10
Dispatch Table Entries
0: Reserved
1: NMI
2: Reserved
3: Reserved
4: Reserved
5: SVC (Supervisor Call Trap)
6: DVC (Divided by Zero Trap)
7: FLG (Flag Trap)
8: BPT (Breakpoint Trap)
9: TRC (Trace Trap)
10: UND (Undefined Instruction Trap)
11: Reserved
12: Reserved
13: Reserved
14: Reserved
15: Reserved
16: INT0 (Reserved)
17: INT1 (Flash EEPROM Program Memory)
18: INT2 (Reserved)
19: INT3 (Reserved)
20: INT4 (Reserved)
21: INT5 (ADC)
22: INT6 (MIWU Interrupt 3)
23: INT7 (MIWU Interrupt 2)
24: INT8 (MIWU Interrupt 1)
25: INT9 (MIWU Interrupt 0)
26: INT10 (USART 2 Tx)
27: INT11 (USART 1Tx)
28: INT12 (Reserved)
29: INT13 (MICROWIRE/SPI Rx/TX)
30: INT14 (ACCESS.bus)
31: INT15 (USART 2 Rx)
32: INT16 (USART 1 Rx)
33: INT17 (Reserved)
34: INT18 (CAN)
35: INT19 (Reserved)
36: INT20 (Reserved)
37: INT21 (Reserved)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16HCS5VJE8 | Microcontroller |
| CR16HCS9VJE7Y | Microcontroller |
| CR16HCS9VJE8Y | Microcontroller |
| CR16HCT5 | |
| CR16HCT5VJE7Y | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16MCT5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MCT5VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16MCT9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| CR16MCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。