參數(shù)資料
型號: CS2200-CP-CZZR
廠商: CIRRUS LOGIC INC
元件分類: XO, clock
英文描述: PHASE LOCKED LOOP, 75 MHz, PDSO10
封裝: 3 MM, LEAD FREE, MO-187, MSOP-10
文件頁數(shù): 11/26頁
文件大?。?/td> 307K
代理商: CS2200-CP-CZZR
CS2200-CP
DS759PP1
19
8. REGISTER DESCRIPTIONS
In IC Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re-
served” registers must maintain their default state to ensure proper functional operation. The default state of each
bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register
Control port mode is entered when the device recognizes a valid chip address input on its IC/SPI serial control pins
and the EnDevCfg1 and EnDevCfg2 bits are set to 1.
8.1
Device I.D. and Revision (Address 01h)
8.1.1
Device Identification (Device[4:0]) - Read Only
I.D. code for the CS2200.
8.1.2
Device Revision (Revision[2:0]) - Read Only
CS2200 revision level.
8.2
Device Control (Address 02h)
8.2.1
Unlock Indicator (Unlock) - Read Only
Indicates the lock state of the PLL.
8.2.2
Auxiliary Output Disable (AuxOutDis)
This bit controls the output driver for the AUX_OUT pin.
7
6
5
432
10
Device4
Device3
Device2
Device1
Device0
Revision2
Revision1
Revision0
Device[4:0]
Device
00000
CS2200.
REVID[2:0]
Revision Level
100
B2.
76543210
Unlock
Reserved
AuxOutDis
ClkOutDis
Unlock
PLL Lock State
0
PLL is Locked.
1
PLL is Unlocked.
AuxOutDis
Output Driver State
0
AUX_OUT output driver enabled.
1
AUX_OUT output driver set to high-impedance.
Application:
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